diff --git a/arch/arm64/boot/dts/phytium/Makefile b/arch/arm64/boot/dts/phytium/Makefile index d57cbc8e189c3..cb6c2f05aea84 100644 --- a/arch/arm64/boot/dts/phytium/Makefile +++ b/arch/arm64/boot/dts/phytium/Makefile @@ -3,6 +3,10 @@ dtb-$(CONFIG_ARCH_PHYTIUM) += pe2204-demo-ddr4-local.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += pe2202-demo-ddr4.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += pe2202-demo-ddr4-local.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += pe2201-demo-ddr4.dtb +dtb-$(CONFIG_ARCH_PHYTIUM) += pd2308-demo-a.dtb +dtb-$(CONFIG_ARCH_PHYTIUM) += pd2308-demo-b.dtb +dtb-$(CONFIG_ARCH_PHYTIUM) += ps2316-devboard-16c-dsk.dtb +dtb-$(CONFIG_ARCH_PHYTIUM) += pd2408-devboard-d4-dsk.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/phytium/pd2308-demo-a.dts b/arch/arm64/boot/dts/phytium/pd2308-demo-a.dts new file mode 100644 index 0000000000000..f658dace2fe48 --- /dev/null +++ b/arch/arm64/boot/dts/phytium/pd2308-demo-a.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS file for Phytium pd2308 devboard + * + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +/dts-v1/; +/memreserve/ 0x80000000 0x10000; + +#include "pd2308.dtsi" + +/{ + model = "Pd2308 DEMO"; + compatible = "phytium,pd2308"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "uart1:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x7b000000>; + numa-node-id = <0x00>; + }; + + memory@01{ + device_type = "memory"; + reg = <0x20 0x00000000 0x0f 0x80000000>; + numa-node-id = <0x00>; + }; +}; + +&uart0 { + status = "ok"; +}; + +&uart1 { + status = "ok"; +}; + +&uart2 { + status = "ok"; +}; + +&uart3 { + status = "ok"; +}; + +&sata0 { + status = "ok"; +}; + +&mmc0 { + bus-width = <0x04>; + max-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + sd-uhs-sdr25; + no-mmc; + status = "okay"; +}; + +&qspi { + status = "ok"; +}; + +&hda { + status = "ok"; +}; + +&can0 { + status = "ok"; +}; + +&can1 { + status = "ok"; +}; + +&i2c0 { + status = "ok"; +}; + +&i2c1 { + status = "ok"; +}; + +&i2c2 { + status = "ok"; +}; + +&gpio0 { + status = "ok"; +}; + +&gpio1 { + status = "ok"; +}; + +&gpio2 { + status = "ok"; +}; + +&gpio3 { + status = "ok"; +}; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; + +&i3c0 { + status = "ok"; +}; + +&i3c1 { + status = "ok"; +}; + +&pwm0 { + phytium,db = <0 0 0 1000 1000 0>; + status = "ok"; +}; + +&pwm1 { + phytium,db = <0 0 0 1000 1000 0>; + status = "ok"; +}; + +&lpc { + status = "ok"; +}; + +&phytmac0 { + phy-mode = "sgmii"; + use-mii; + status = "ok"; +}; + +&phytmac1 { + phy-mode = "usxgmii"; + status = "ok"; + fixed-link { + speed = <0x2710>; + full-duplex; + }; +}; diff --git a/arch/arm64/boot/dts/phytium/pd2308-demo-b.dts b/arch/arm64/boot/dts/phytium/pd2308-demo-b.dts new file mode 100644 index 0000000000000..fa984a1455c37 --- /dev/null +++ b/arch/arm64/boot/dts/phytium/pd2308-demo-b.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS file for Phytium pd2308 devboard + * + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +/dts-v1/; +/memreserve/ 0x80000000 0x10000; + +#include "pd2308.dtsi" + +/{ + model = "Pd2308 DEMO"; + compatible = "phytium,pd2308"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "uart1:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x7b000000>; + numa-node-id = <0x00>; + }; + + memory@01{ + device_type = "memory"; + reg = <0x20 0x00000000 0x0f 0x80000000>; + numa-node-id = <0x00>; + }; +}; + +&uart1 { + status = "ok"; +}; + +&uart0 { + status = "ok"; +}; + +&sata0 { + status = "ok"; +}; + +&mmc0 { + bus-width = <0x08>; + max-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + sd-uhs-sdr25; + no-mmc; + status = "okay"; +}; + +&qspi { + status = "ok"; +}; + +&can0 { + status = "ok"; +}; + +&can1 { + status = "ok"; +}; + +&i2c1 { + status = "ok"; +}; + +&i2c2 { + status = "ok"; +}; + +&gpio0 { + status = "ok"; +}; + +&gpio1 { + status = "ok"; +}; + +&gpio2 { + status = "ok"; +}; + +&gpio3 { + status = "ok"; +}; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; + +&i3c0 { + status = "ok"; +}; + +&i3c1 { + status = "ok"; +}; + +&pwm0 { + phytium,db = <0 0 0 1000 1000 0>; + status = "ok"; +}; + +&phytmac0 { + status = "ok"; + phy-mode = "uxsgmii"; + fixed-link { + speed = <10000>; + full-duplex; + }; +}; + +&phytmac1 { + status = "ok"; + phy-mode = "uxsgmii"; + fixed-link { + speed = <10000>; + full-duplex; + }; +}; diff --git a/arch/arm64/boot/dts/phytium/pd2308.dtsi b/arch/arm64/boot/dts/phytium/pd2308.dtsi new file mode 100644 index 0000000000000..ecc48935fc56a --- /dev/null +++ b/arch/arm64/boot/dts/phytium/pd2308.dtsi @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Phytium pd308 SoC + * + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +#include + +/ { + compatible = "phytium,pd2308"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &phytmac0; + ethernet1 = &phytmac1; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + numa-node-id = <0x00000000>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + numa-node-id = <0x0>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + clocks = <&scmi_dvfs 2>; + numa-node-id = <0x0>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + clocks = <&scmi_dvfs 3>; + numa-node-id = <0x0>; + }; + cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; + clocks = <&scmi_dvfs 4>; + numa-node-id = <0x0>; + }; + cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + enable-method = "psci"; + clocks = <&scmi_dvfs 5>; + numa-node-id = <0x0>; + }; + cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10200>; + enable-method = "psci"; + clocks = <&scmi_dvfs 6>; + numa-node-id = <0x0>; + }; + cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10300>; + enable-method = "psci"; + clocks = <&scmi_dvfs 7>; + numa-node-id = <0x0>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&mbox 0 &mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_hpri &cpu_scp_lpri>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + }; + + thermal-zones { + status = "disabled"; + sensor0 { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scmi_sensors0 0>; + }; + + sensor1 { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scmi_sensors0 1>; + }; + }; + + gic: interrupt-controller@36800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x36800000 0 0x20000>, /* GICD */ + <0x0 0x36860000 0 0x100000>; /* GICR */ + + interrupts = ; + phandle = <0x1>; + + its: gic-its@36840000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x36840000 0x0 0x20000>; + phandle = <0x3>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <50000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sysclk_250mhz: clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + sysclk_50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + sysclk_100mhz: clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + sysclk_200mhz: clk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + sysclk_600mhz: clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + sysclk_1200mhz: clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1200000000>; + }; + + sysclk_300mhz: clk300mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + }; + + smmu: iommu@36000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x36000000 0x0 0x800000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mmc0: mmc@28000000 { + compatible = "phytium,mci"; + reg = <0x0 0x28000000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + }; + + hda: hda@28002000 { + compatible = "phytium,hda"; + reg = <0 0x28002000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_48mhz>; + clock-names = "phytium_hda_clk"; + status = "disabled"; + }; + + qspi: spi@28004000 { + compatible = "phytium,qspi-nor"; + reg = <0x0 0x28004000 0x0 0x1000>, + <0x0 0x00 0x0 0x10000000>; + reg-names = "qspi", "qspi_mm"; + clocks = <&sysclk_50mhz>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x00>; + spi-rx-bus-width = <1>; + spi-max-frequency = <5000000>; + }; + }; + + i2s0: i2s@28005000 { + compatible = "phytium,i2s"; + reg = <0x0 0x28005000 0x0 0x1000>, + <0x0 0x28001000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-lsd"; + status = "disabled"; + }; + + can0: can@28006000 { + compatible = "phytium,canfd"; + reg = <0x0 0x28006000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_300mhz>; + clock-names = "can_clk"; + tx-fifo-depth = <64>; + rx-fifo-depth = <64>; + status = "disabled"; + }; + + can1: can@28007000 { + compatible = "phytium,canfd"; + reg = <0x0 0x28007000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_300mhz>; + clock-names = "can_clk"; + tx-fifo-depth = <64>; + rx-fifo-depth = <64>; + status = "disabled"; + }; + + uart0: uart@28008000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28008000 0x0 0x1000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@28009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x28009000 0x0 0x1000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@2800a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800a000 0x0 0x1000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: uart@2800b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800b000 0x0 0x1000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@2800c000 { + compatible = "phytium,i2c"; + reg = <0x0 0x2800c000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + i2c1: i2c@2800d000 { + compatible = "phytium,i2c"; + reg = <0x0 0x2800d000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + i2c2: i2c@28021000 { + compatible = "phytium,i2c"; + reg = <0x0 0x28021000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + gpio0: gpio@2800e000 { + compatible = "phytium,gpio"; + reg = <0x0 0x2800e000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + gpio1: gpio@2800f000 { + compatible = "phytium,gpio"; + reg = <0x0 0x2800f000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + gpio2: gpio@28010000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28010000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + gpio3: gpio@28011000 { + compatible = "phytium,gpio"; + reg = <0x0 0x28011000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + spi0: spi@28012000 { + compatible = "phytium,spi"; + interrupts = ; + reg = <0x0 0x28012000 0x0 0x1000>; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + global-cs = <1>; + + spidev@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <0x00b71b00>; + reg = <0>; + }; + }; + + spi1: spi@28013000 { + compatible = "phytium,spi"; + interrupts = ; + reg = <0x0 0x28013000 0x0 0x1000>; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + status = "disabled"; + }; + + watchdog0: watchdog@28014000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28014000 0x0 0x1000>, + <0x0 0x28015000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + }; + + watchdog1: watchdog@28016000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x28016000 0x0 0x1000>, + <0x0 0x28017000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + }; + + i3c0: i3c-master@28018000 { + compatible = "phytium,cdns-i3c-master"; + regs = <0x0 0x28018000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>, <&sysclk_50mhz>; + clock-names = "pclk", "sysclk"; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-hz = <400000>; + i3c-scl-hz = <1000000>; + status = "disabled"; + }; + + i3c1: i3c-master@28019000 { + compatible = "phytium,cdns-i3c-master"; + regs = <0x0 0x28019000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>, <&sysclk_50mhz>; + clock-names = "pclk", "sysclk"; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-hz = <400000>; + i3c-scl-hz = <1000000>; + status = "disabled"; + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + pwm0: pwm@2801a000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2801a000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + pwm1: pwm@2801b000 { + compatible = "phytium,pwm"; + reg = <0x0 0x2801b000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + tacho0: tacho@2801c000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2801c000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + tacho1: tacho@2801d000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2801d000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + tacho2: tacho@2801e000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2801e000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + tacho3: tacho@2801f000 { + compatible = "phytium,tacho"; + reg = <0x0 0x2801f000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + sce0: crypto@36cc0000 { + compatible = "phytium,sce"; + reg = <0x0 0x36cc0000 0x0 0x4000>; + interrupts = ; + host-number = <2>; + status = "disabled"; + }; + + phytmac0: eth0@36ce0000 { + compatible = "cdns,phytium-gem-3.0"; + reg = <0 0x36ce0000 0x0 0x2000>; + interrupts = , + , + , + ; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk","tsu_clk"; + clocks = <&sysclk_250mhz>, <&sysclk_250mhz>,<&sysclk_250mhz>, + <&sysclk_250mhz>,<&sysclk_300mhz>; + magic-packet; + dma-coherent; + queue-number = <0x04>; + status = "disabled"; + }; + + + phytmac1: eth1@36ce2000 { + compatible = "cdns,phytium-gem-3.0"; + reg = <0 0x36ce2000 0x0 0x2000>; + interrupts = , + , + , + ; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk","tsu_clk"; + clocks = <&sysclk_250mhz>, <&sysclk_250mhz>,<&sysclk_250mhz>, + <&sysclk_250mhz>,<&sysclk_300mhz>; + magic-packet; + dma-coherent; + queue-number = <0x04>; + status = "disabled"; + }; + + sata0: sata@36ce5000 { + compatible = "generic-ahci"; + reg = <0x0 0x36ce5000 0x0 0x1000>; + interrupts = ; + status = "disabled"; + }; + + lpc: lpc@20000000 { + compatible = "phytium,i8042"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x20000000 0x0 0x100>; + interrupts = ; + lpc_version = <1>; + status = "disabled"; + }; + + mbox: mailbox@36d00000 { + compatible = "phytium,mbox"; + reg = <0x0 0x36d00000 0x0 0x1000>; + interrupts = ; + #mbox-cells = <1>; + status = "disabled"; + }; + + sram: sram@36d04000 { + compatible = "mmio-sram"; + reg = <0x0 0x36d04000 0x0 0x2000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x36d04000 0x2000>; + status = "disabled"; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x1000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@1 { + compatible = "arm,scmi-shmem"; + reg = <0x1400 0x400>; + }; + }; + + mio: mio0@28022000 { + compatible = "phytium,mio"; + reg = <0x00 0x28022000 0x00 0x1000>; + interrupts = <0 93 4>; + clocks = <&sysclk_50mhz &sysclk_50mhz>; + clock-names = "mio_clk"; + status = "disabled"; + }; + + pcie: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + msi-parent = <&its>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic + 0x0 0x0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x2 &gic + 0x0 0x0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x3 &gic + 0x0 0x0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x4 &gic + 0x0 0x0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x1000000 0x00 0x00 0x0 0x50000000 0x0 0xf00000>, + <0x2000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x3000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + dma-ranges = <0x43000000 0x00 0x00 0x00 0x00 0x1000 0x00>; + iommu-map = <0x0 &smmu 0x0 0x10000>; + io-upper = <0x50005000>; + dma-coherent; + }; + }; +}; diff --git a/arch/arm64/boot/dts/phytium/pd2408-devboard-d4-dsk.dts b/arch/arm64/boot/dts/phytium/pd2408-devboard-d4-dsk.dts new file mode 100644 index 0000000000000..ce47406ebbe9d --- /dev/null +++ b/arch/arm64/boot/dts/phytium/pd2408-devboard-d4-dsk.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS file for Phytium Pd2408 Development Board + * + * Copyright (C) 2018-2023, Phytium Technology Co., Ltd. + */ + +/dts-v1/; +/memreserve/ 0x80000000 0x10000; + +#include "pd2408-generic-psci-soc.dtsi" + +/{ + model = "Phytium Pd2408 Development Board"; + compatible = "phytium,pd2408-devboard", "phytium,pd2408"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "uart1:115200n8"; + }; + + memory@00{ + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + + +&uart0 { + status = "ok"; +}; + +&uart1 { + status = "ok"; +}; + +&uart2 { + status = "ok"; +}; + +&mmc0 { + bus-width = <0x00000008>; + max-frequency = <1000000>; + cap-mmc-hw-reset; + cap-mmc-highspeed; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "ok"; +}; + +&i2c1 { + status = "ok"; +}; + +&i2c2 { + status = "ok"; +}; + +&i2c3 { + status = "ok"; +}; + +&sata { + status = "ok"; +}; + +&usb3_0 { + status = "ok"; +}; + +&usb3_1 { + status = "ok"; +}; + +&usb3_2 { + status = "ok"; +}; + +&usb3_3 { + status = "ok"; +}; + +&usb3_4 { + status = "ok"; +}; + +&usb2_0 { + status = "ok"; +}; + +&usb2_1 { + status = "ok"; +}; + +&pcie { + status = "ok"; +}; + +&qspi0 { + status = "ok"; +}; + +&spi0 { + status = "ok"; +}; + +&spi1 { + status = "ok"; +}; + +&gpio0 { + status = "ok"; +}; + +&gpio1 { + status = "ok"; +}; + +&pwm0 { + phytium,db = <0 0 0 1000 1000 0>; + status = "ok"; +}; + +&i2s0 { + status = "ok"; +}; + +&gmac0 { + status = "ok"; +}; + +&npu { + status = "ok"; +}; + +&virt_gmac0 { + status = "ok"; +}; + +&virt_i2s0 { + status = "ok"; +}; + +&virt_gmac0 { + status = "ok"; +}; + +&virt_uart0 { + status = "ok"; +}; + +&virt_uart1 { + status = "ok"; +}; + +&virt_uart2 { + status = "ok"; +}; + +&virt_mmc0 { + bus-width = <0x00000008>; + max-frequency = <1000000>; + cap-mmc-hw-reset; + cap-mmc-highspeed; + no-sdio; + no-sd; + non-removable; + status = "ok"; +}; + +&virt_i2c0 { + status = "ok"; +}; + +&virt_i2c1 { + status = "ok"; +}; + +&virt_i2c2 { + status = "ok"; +}; + +&virt_i2c3 { + status = "ok"; +}; + +&virt_spi0 { + status = "ok"; +}; + +&virt_spi1 { + status = "ok"; +}; + diff --git a/arch/arm64/boot/dts/phytium/pd2408-generic-psci-soc.dtsi b/arch/arm64/boot/dts/phytium/pd2408-generic-psci-soc.dtsi new file mode 100644 index 0000000000000..35d93f716a152 --- /dev/null +++ b/arch/arm64/boot/dts/phytium/pd2408-generic-psci-soc.dtsi @@ -0,0 +1,1065 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Phytium Pd2408 SoC + * + * Copyright (C) 2018-2023, Phytium Technology Co., Ltd. + */ + +#include + +/ { + compatible = "phytium,pd2408"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + buffer@0 { + no-map; + reg = <0x21 0x10000000 0x0 0x8000000>; + phandle = <0x19>; + }; + + buffer@10 { + no-map; + reg = <0x21 0x20000000 0x0 0x40000000>; + phandle = <0x18>; + }; + + buffer@20 { + no-map; + reg = <0x21 0x60000000 0x0 0x40000000>; + phandle = <0x20>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + virt_sound_card: virt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "phytium,e2000-i2s-audio"; + simple-audio-card,pin-switches = "mic-in"; + simple-audio-card,widgets = "Microphone","mic-in"; +// simple-audio-card,routing = "MIC2","mic-in"; + simple-audio-card,cpu { + sound-dai = <&virt_i2s0>; + }; + simple-audio-card,codec{ + sound-dai = <&virt_codec0>; + }; + }; + + sound_card: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "phytium,e2000-i2s-audio"; + simple-audio-card,pin-switches = "mic-in"; + simple-audio-card,widgets = "Microphone","mic-in"; + //simple-audio-card,routing = "MIC2","mic-in"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec{ + sound-dai = <&codec0>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + + core0 { + cpu = <&cpu_l0>; + }; + + core1 { + cpu = <&cpu_l1>; + }; + + core2 { + cpu = <&cpu_l2>; + }; + + core3 { + cpu = <&cpu_b0>; + }; + + }; + + cluster1 { + core0 { + cpu = <&cpu_l3>; + }; + + core1 { + cpu = <&cpu_l4>; + }; + + core2 { + cpu = <&cpu_l5>; + }; + + core3 { + cpu = <&cpu_b1>; + }; + }; + + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 0>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 1>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 2>; + }; + + cpu_b0: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 3>; + }; + + cpu_l3: cpu@10000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 4>; + }; + + cpu_l4: cpu@10100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 5>; + }; + + cpu_l5: cpu@10200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10200>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 6>; + }; + + cpu_b1: cpu@10300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10300>; + enable-method = "psci"; + numa-node-id = <0>; + clocks = <&scmi_dvfs 7>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&mbox 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_hpri>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_power: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + }; + + thermal_zones: thermal-zones { + sensor0 { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scmi_sensors0 0>; + + trips { + threshod: trip-point@0 { + temperature = <75000>; + hysteresis = <0>; + type = "passive"; + }; + target: trip-point@1 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor1 { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&scmi_sensors0 1>; + + trips { + threshod1: trip-point@0 { + temperature = <75000>; + hysteresis = <0>; + type = "passive"; + }; + target1: trip-point@1 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + cpu_crit1: cpu_crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + gic: interrupt-controller@26800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x26800000 0 0x10000>, /* GICD */ + <0x0 0x26860000 0 0x100000>, /* GICR */ + <0x0 0x26970000 0 0x10000>, /* GICC */ + <0x0 0x26980000 0 0x10000>, /* GICH */ + <0x0 0x26990000 0 0x10000>; /* GICV */ + interrupts = ; + + its: gic-its@26840000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x26840000 0x0 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <48000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clk250mhz: clk250mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + sysclk_50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + sysclk_100mhz: clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + sysclk_600mhz: clk600mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + sysclk_1200mhz: clk1200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1200000000>; + }; + + }; + + smmu: iommu@26000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x26000000 0x0 0x800000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + ranges; + + uart0: uart@18001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x18001000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@18002000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x18002000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@18003000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x18003000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + virt_uart0: uart@27011000 { + compatible = "phytium,ftd35"; + reg = <0x0 0x27011000 0x0 0x1000>, + <0x0 0x26fe4000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + virt_uart1: uart@27012000 { + compatible = "phytium,ftd35"; + reg = <0x0 0x27012000 0x0 0x1000>, + <0x0 0x26fe5000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + virt_uart2: uart@27013000 { + compatible = "phytium,ftd35"; + reg = <0x0 0x27013000 0x0 0x1000>, + <0x0 0x26fe6000 0x0 0x1000>; + baud = <3000000>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysclk_100mhz &sysclk_100mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + mmc0: mmc@18005000 { + compatible = "phytium,mci"; + reg = <0x0 0x18005000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + }; + + virt_mmc0: mmc@27018000 { + compatible = "phytium,mci_iop"; + reg = <0x0 0x27018000 0x0 0x1000>, + <0x0 0x26fea000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "phytium_mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@1800a000 { //smbus0 + compatible = "phytium,i2c"; + reg = <0x0 0x1800a000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1800b000 { //smbus1 + compatible = "phytium,i2c"; + reg = <0x0 0x1800b000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1800c000 { //pmbus0 + compatible = "phytium,i2c"; + reg = <0x0 0x1800c000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + anx7411@2c { + compatible = "analogix,anx7411"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-gpios = <0xf 0x00 0x4>; + port@0 { + reg = <0>; + con_usb_c_ep:endpoint{ + remote-endpoint = < &usb_ep>; + }; + }; + orientation_switch { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + anx7411_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&anx7411_switch>; + }; + }; + }; + mode_switch { + status = "okay"; + mode-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + anx7411_dp_altmode_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&anx7411_mux>; + }; + }; + }; + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + anx7411_switch: endpoint { + remote-endpoint = <&anx7411_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + anx7411_mux: endpoint { + remote-endpoint = <&anx7411_dp_altmode_switch>; + }; + }; + }; + }; + + }; + codec0: es8336@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8336"; + reg = <0x10>; + }; + }; + + i2c3: i2c@1800d000 { //pmbus1 + compatible = "phytium,i2c"; + reg = <0x0 0x1800d000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + virt_i2c0: i2c@27019000 { //smbus0 + compatible = "phytium,i2c_iop"; + reg = <0x0 0x27019000 0x0 0x1000>, + <0x0 0x26feB000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + virt_i2c1: i2c@2701a000 { //smbus1 + compatible = "phytium,i2c_iop"; + reg = <0x0 0x2701a000 0x0 0x1000>, + <0x0 0x26fec000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + virt_i2c2: i2c@2701b000 { //pmbus0 + compatible = "phytium,i2c_iop"; + reg = <0x0 0x2701b000 0x0 0x1000>, + <0x0 0x26feD000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + virt_i2c3: i2c@2701c000 { //pmbus1 + compatible = "phytium,i2c_iop"; + reg = <0x0 0x2701c000 0x0 0x1000>, + <0x0 0x26fee000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + sata: sata@26fd4000 { + compatible = "generic-ahci"; + reg = <0x0 0x26fd4000 0x0 0x1000>; + interrupts = ; + iommus = <&smmu 0xf000>; + status = "disabled"; + }; + + sce: sce@26ec0000 { + compatible = "phytium,scev2"; + reg = <0x0 0x26ec0000 0x0 0x5000 0x0 0x26ec5000 0x0 0x1000>; + interrupts = , + , + ; + power-domains = <&scmi_power 0x22>; + status = "disabled"; + }; + +//PGU USB3 + + usb3_0: usb0@26ee8000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26ee8000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + usb3_1: usb2@26f08000 { + compatible = "phytium,usb2_xhci"; + reg = <0x0 0x26f00000 0x0 0x4000>, + <0x0 0x26f04000 0x0 0x4000>, + <0x0 0x26f08000 0x0 0x18000>; + reg-names = "otg", "dev", "xhci"; + interrupts = , //host & device interrupt + ; //otg interrupt + interrupt-names = "generic","otg"; + status = "disabled"; + usb-role-switch; + port{ + usb_ep:endpoint { + remote-endpoint= <&con_usb_c_ep>; + }; + }; + }; + + usb3_2: usb1@26f28000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26f28000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + + usb3_3: usb3@26f48000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26f48000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + usb3_4: usb4@26f68000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26f68000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + usb2_0: usb0@26f88000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26f88000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + usb2_1: usb1@26fa8000 { + compatible = "phytium,pe220x-xhci"; + reg = <0x0 0x26fa8000 0x0 0x18000>; + interrupts = ; + status = "disabled"; + }; + + qspi0: qspi@18006000 { + compatible = "phytium,qspi-nor"; + reg = <0x0 0x18006000 0x0 0x1000>, + <0x0 0x0 0x0 0x0fffffff>; + reg-names = "qspi", "qspi_mm"; + clocks = <&sysclk_600mhz>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x00>; + spi-rx-bus-width = <1>; + spi-max-frequency = <50000000>; + }; + }; + + spi0: spi@18010000 { + compatible = "phytium,spi"; + reg = <0x0 0x18010000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@18011000 { + compatible = "phytium,spi"; + reg = <0x0 0x18011000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + virt_spi0: spi@27014000 { + compatible = "phytium,spi-iop"; + reg = <0x0 0x27014000 0x0 0x1000>, + <0x0 0x26fe7000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + virt_spi1: spi@27015000 { + compatible = "phytium,spi-iop"; + reg = <0x0 0x27015000 0x0 0x1000>, + <0x0 0x26fe8000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + watchdog0: watchdog@18012000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x18013000 0x0 0x1000>, + <0x0 0x18012000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + status = "disabled"; + }; + + watchdog1: watchdog@18014000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x18015000 0x0 0x1000>, + <0x0 0x18014000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + status = "disabled"; + }; + + + mbox: mailbox@26fc0000 { + compatible = "phytium,mbox"; + reg = <0x0 0x26fc0000 0x0 0x4000>; + interrupts = ; + #mbox-cells = <1>; + }; + + sram: sram@26fc4000 { + compatible = "mmio-sram"; + reg = <0x0 0x26fc4000 0x0 0x2000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x26fc4000 0x2000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x1000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@1 { + compatible = "arm,scmi-shmem"; + reg = <0x1400 0x400>; + }; + }; + + gpio0: gpio@18007000 { + compatible = "phytium,gpio"; + reg = <0x0 0x18007000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + gpio1: gpio@18008000 { + compatible = "phytium,gpio"; + reg = <0x0 0x18008000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta { + compatible = "phytium,gpio-port"; + reg = <0>; + ngpios = <16>; + }; + }; + + pwm0: pwm@1800e000 { + compatible = "phytium,pwm"; + reg = <0x0 0x1800e000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + status = "disabled"; + }; + + gpu@26c00000 { + compatible = "phytium,ftg340"; + interrupts = <0x0 0x1a 0x4>; + interrupt-names = "core_major"; + reg = <0x0 0x26c00000 0x0 0x40000>; + memory-region = <0x18>; + power-domains = <&scmi_power 0x19 &scmi_power 0x1a &scmi_power 0x1b &scmi_power 0x1c &scmi_power 0x1d>; + }; + + dcFTD330@0x26ca0000 { + compatible = "phytium,dc-1.0"; + reg = <0x0 0x26ca0000 0x0 0x1e000 0x00 0x26fcc080 0x00 0x20>; + interrupts = <0x0 0x37 0x4 0x0 0x3a 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4>; + pipe_mask = [03]; + edp_mask = [00]; + overlay_enable = <0x00>; + memory-region = <0x19>; + water_mark = <0x5666 0x5666 0x5666>; + qos = <0xf0 0xf0 0xf0>; + phy_mode = <0x01 0x01 0x01>; + power-domains = <&scmi_power 0x1f &scmi_power 0x20>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + vpu { + compatible = "phytium,vpu"; + reg = <0x0 0x26c88000 0x0 0x10000 0x0 0x26fcc0a0 0x0 0x40>; + interrupts = <0x0 0x1c 0x4>, <0x0 0x1d 0x4>; + memory-region = <0x20>; + power-domains = <&scmi_power 0x25 &scmi_power 0x26>; + }; + + + i2s_dp0@26cbe000 { + compatible = "phytium,i2s"; + reg = <0x0 0x26cbe000 0x0 0x1000 0x0 0x26cbf000 0x0 0x1000>; + interrupts = <0 68 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp0"; + }; + + i2s_dp1@0x26cc0000 { + compatible = "phytium,i2s"; + reg = <0x0 0x26cc0000 0x0 0x1000 0x0 0x26cc1000 0x0 0x1000>; + interrupts = <0 69 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp1"; + }; + + i2s_dp0@0x26cc2000 { + compatible = "phytium,i2s"; + reg = <0x0 0x26cc2000 0x0 0x1000 0x0 0x26cc3000 0x0 0x1000>; + interrupts = <0 70 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp2"; + }; + + virt_i2s_dp0@0x2701f000 { + compatible = "phytium,virt-i2s"; + reg = <0x0 0x2701f000 0x0 0x1000>, + <0x0 0x26fe0000 0x0 0x1000>, + <0x0 0x26cbf000 0x0 0x1000>; + interrupts = <0 68 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp0"; + }; + + virt_i2s_dp1@0x27020000 { + compatible = "phytium,virt-i2s"; + reg = <0x0 0x27020000 0x0 0x1000>, + <0x0 0x26fe1000 0x0 0x1000>, + <0x0 0x26cc1000 0x0 0x1000>; + interrupts = <0 69 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp1"; + }; + + virt_i2s_dp2@0x27021000 { + compatible = "phytium,virt-i2s"; + reg = <0x0 0x27021000 0x0 0x1000>, + <0x0 0x26fe2000 0x0 0x1000>, + <0x0 0x26cc3000 0x0 0x1000>; + interrupts = <0 70 4>; + clocks = <&sysclk_600mhz>; + clock-names = "i2s_clk"; + dai-name = "phytium-i2s-dp2"; + }; + + pmdk_dp { + compatible = "phytium,pmdk-dp"; + num-dp = <0x00000003>; + }; + + i2s0: i2s@18009000 { + compatible = "phytium,i2s"; + reg = <0x0 0x18009000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "i2s_clk"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + virt_i2s0: i2s@27010000 { + compatible = "phytium,virt-i2s"; + #sound-dai-cells = <0x0>; + reg = <0x0 0x27010000 0x0 0x800>, + <0x0 0x26fe3000 0x0 0x100>, + <0x0 0x18000000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_1200mhz>; + clock-names = "i2s_clk"; + status = "disabled"; + }; + + virt_codec0: codec@27010800 { + compatible = "phytium,virt-codec"; + #sound-dai-cells = <0x0>; + reg = <0x0 0x27010800 0x0 0x800>, + < 0x0 0x26fe3100 0x0 0x100>; + interrupts = ; + status = "disabled"; + }; + + virt_gmac0: eth0@2701d000 { + compatible = "phytium,gmac-2.0"; + reg = <0x0 0x2701d000 0x0 0x2000>, + <0x0 0x26fef000 0x0 0x1000>; + interrupts = , + ; + queue-number = <0x2>; + phy-mode = "sgmii"; + use-mii; + dma-coherent; + status = "disabled"; + }; + + gmac0: eth0@26fd0000 { + compatible = "phytium,gmac-1.1"; + reg = <0x0 0x26fd0000 0x0 0x2000>; + interrupts = , + ; + queue-number = <0x2>; + phy-mode = "sgmii"; + use-mii; + dma-coherent; + status = "disabled"; + }; + + npu:npu@26d00000 { + compatible = "phytium,npu"; + reg = <0x0 0x26d00000 0x0 0x80000 + 0x0 0x26fcc060 0x0 0x20>;//power manage + interrupts = <0 74 4>; + dma-mask=<0xff 0xffffffff>; + power-domains = <&scmi_power 0x18>; + status = "disabled"; + }; + + pcie: pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + msi-parent = <&its>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x44000000 0x0 0x01000000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x03000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + iommu-map = <0x0 &smmu 0x0 0x10000>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/phytium/ps2316-devboard-16c-dsk.dts b/arch/arm64/boot/dts/phytium/ps2316-devboard-16c-dsk.dts new file mode 100644 index 0000000000000..ff93231a5c02b --- /dev/null +++ b/arch/arm64/boot/dts/phytium/ps2316-devboard-16c-dsk.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS file for Phytium Ps2316 devboard + * + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +/dts-v1/; +/memreserve/ 0x80000000 0x10000; + +#include "ps2316-generic-psci-soc.dtsi" + +/{ + model = "Ps2316 Development Board"; + compatible = "phytium,ps2316"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "uart1:115200n8"; + }; + + memory@00{ + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x00000000>; /* Updated by bootloader */ + }; +}; + + +&uart0 { + status = "ok"; +}; + +&uart1 { + status = "ok"; +}; + +&uart2 { + status = "ok"; +}; + +&i2c0 { + status = "ok"; +}; + +&i2c1 { + status = "ok"; +}; + +&i2c2 { + status = "ok"; +}; + +&i3c { + status = "ok"; +}; + +&watchdog0 { + status = "ok"; +}; + +&watchdog1 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/phytium/ps2316-generic-psci-soc.dtsi b/arch/arm64/boot/dts/phytium/ps2316-generic-psci-soc.dtsi new file mode 100644 index 0000000000000..b42ada2374f97 --- /dev/null +++ b/arch/arm64/boot/dts/phytium/ps2316-generic-psci-soc.dtsi @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Phytium Ps2316 SoC + * + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +#include + +/ { + compatible = "phytium,ps2316"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x3>; + }; + + core1 { + cpu = <0x4>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x5>; + }; + + core1 { + cpu = <0x6>; + }; + }; + + cluster2 { + + core0 { + cpu = <0x7>; + }; + + core1 { + cpu = <0x8>; + }; + }; + + cluster3 { + + core0 { + cpu = <0x9>; + }; + + core1 { + cpu = <0xa>; + }; + }; + + cluster4 { + + core0 { + cpu = <0xb>; + }; + + core1 { + cpu = <0xc>; + }; + }; + + cluster5 { + + core0 { + cpu = <0xd>; + }; + + core1 { + cpu = <0xe>; + }; + }; + + cluster6 { + + core0 { + cpu = <0xf>; + }; + + core1 { + cpu = <0x10>; + }; + }; + + cluster7 { + + core0 { + cpu = <0x11>; + }; + + core1 { + cpu = <0x12>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x3>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x4>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x20000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x5>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x30000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x6>; + }; + + cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x40000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x7>; + }; + + cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x50000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x8>; + }; + + cpu@6 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x60000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x9>; + }; + + cpu@7 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x70000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xa>; + }; + + cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x80000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xb>; + }; + + cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x90000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xc>; + }; + + cpu@10 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xa0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xd>; + }; + + cpu@11 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xb0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xe>; + }; + + cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xc0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0xf>; + }; + + cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xd0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x10>; + }; + + cpu@14 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xe0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x11>; + }; + + cpu@15 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0xf0000>; + enable-method = "psci"; + numa-node-id = <0>; + phandle = <0x12>; + }; + }; + + gic: interrupt-controller@22000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0x22000000 0 0x10000>, /* GICD */ + <0x0 0x220c0000 0 0x200000>; /* GICR */ + interrupts = ; + + its: gic-its@220A0000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x220a0000 0x0 0x20000>; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <1000000000>; + }; + + clocks { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + sysclk_50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2faf080>; + }; + + sysclk_100mhz: clk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + ranges; + + uart0: uart@20000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x20000000 0x0 0x1000>; + baud = <115200>; + reg-shift = <0x2>; + reg-io-width = <0x4>; + interrupts = ; + clocks = <&sysclk_50mhz &sysclk_50mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@20001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x20001000 0x0 0x1000>; + baud = <115200>; + reg-shift = <0x2>; + reg-io-width = <0x4>; + interrupts = ; + clocks = <&sysclk_50mhz &sysclk_50mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@20002000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x20002000 0x0 0x1000>; + baud = <115200>; + reg-shift = <0x2>; + reg-io-width = <0x4>; + interrupts = ; + clocks = <&sysclk_50mhz &sysclk_50mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@20003000 { + compatible = "phytium,i2c"; + reg = <0x0 0x20003000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20004000 { + compatible = "phytium,i2c"; + reg = <0x0 0x20004000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20005000 { + compatible = "phytium,i2c"; + reg = <0x0 0x20005000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c: i3c-master@21000000 { + compatible = "phytium,cdns-i3c-master"; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_100mhz>, <&sysclk_100mhz>; + clock-names = "pclk", "sysclk"; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-hz = <400000>; + i3c-scl-hz = <1000000>; + status = "disabled"; + }; + + watchdog0: watchdog@1a102000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x1a103000 0x0 0x1000>, + <0x0 0x1a102000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + status = "disabled"; + }; + + watchdog1: watchdog@1a104000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x1a105000 0x0 0x1000>, + <0x0 0x1a104000 0x0 0x1000>; + interrupts = ; + timeout-sec = <30>; + status = "disabled"; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + msi-parent = <&its>; + bus-range = <0x0 0xff>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 54 0x4>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 53 0x4>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 52 0x4>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 51 0x4>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x50000000 0x00 0x00F00000>, + <0x02000000 0x00 0x58000000 0x00 0x58000000 0x00 0x08000000>, + <0x43000000 0x400 0x00000000 0x400 0x00000000 0x100 0x00000000>; + status = "okay"; + }; + }; + +};