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[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVInstrFormatsV.td. NFC (llvm#179348)
This avoids repeating the splitting into mew/width in multiple places. --------- Co-authored-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
1 parent e0d922e commit 9f47cae

2 files changed

Lines changed: 46 additions & 55 deletions

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‎llvm/lib/Target/RISCV/RISCVInstrFormatsV.td‎

Lines changed: 23 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -162,90 +162,89 @@ class RVInstVUnaryRd<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
162162
let RVVConstraint = NoConstraint;
163163
}
164164

165-
class RVInstVLoadBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
165+
class RVInstVLoadBase<bits<3> nf, RISCVWidth width, RISCVMOP mop,
166166
dag outs, dag ins, string opcodestr, string argstr>
167167
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
168168
bits<5> rs1;
169169
bits<5> vd;
170170
bit vm;
171171

172172
let Inst{31-29} = nf;
173-
let Inst{28} = mew;
173+
let Inst{28} = width.Value{3};
174174
let Inst{27-26} = mop.Value;
175175
let Inst{25} = vm;
176176
// Inst{24-20} provided by subclasses
177177
let Inst{19-15} = rs1;
178-
let Inst{14-12} = width;
178+
let Inst{14-12} = width.Value{2-0};
179179
let Inst{11-7} = vd;
180180
let Inst{6-0} = OPC_LOAD_FP.Value;
181181

182182
let Uses = [VL, VTYPE];
183183
let RVVConstraint = VMConstraint;
184184
}
185185

186-
class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop, bits<3> width, dag outs,
186+
class RVInstVLU<bits<3> nf, RISCVWidth width, RISCVLUMOP lumop, dag outs,
187187
dag ins, string opcodestr, string argstr>
188-
: RVInstVLoadBase<nf, mew, MOPLDUnitStride, width, outs, ins, opcodestr,
188+
: RVInstVLoadBase<nf, width, MOPLDUnitStride, outs, ins, opcodestr,
189189
argstr> {
190190
let Inst{24-20} = lumop.Value;
191191
}
192192

193-
class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
194-
dag outs, dag ins, string opcodestr, string argstr>
195-
: RVInstVLoadBase<nf, mew, MOPLDStrided, width, outs, ins, opcodestr,
196-
argstr> {
193+
class RVInstVLS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
194+
string opcodestr, string argstr>
195+
: RVInstVLoadBase<nf, width, MOPLDStrided, outs, ins, opcodestr, argstr> {
197196
bits<5> rs2;
198197

199198
let Inst{24-20} = rs2;
200199
}
201200

202-
class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
203-
dag outs, dag ins, string opcodestr, string argstr>
204-
: RVInstVLoadBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
201+
class RVInstVLX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
202+
string opcodestr, string argstr>
203+
: RVInstVLoadBase<nf, width, mop, outs, ins, opcodestr, argstr> {
205204
bits<5> vs2;
206205

207206
let Inst{24-20} = vs2;
208207
}
209208

210-
class RVInstVStoreBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
211-
dag outs, dag ins, string opcodestr, string argstr>
209+
class RVInstVStoreBase<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs,
210+
dag ins, string opcodestr, string argstr>
212211
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
213212
bits<5> rs1;
214213
bits<5> vs3;
215214
bit vm;
216215

217216
let Inst{31-29} = nf;
218-
let Inst{28} = mew;
217+
let Inst{28} = width.Value{3};
219218
let Inst{27-26} = mop.Value;
220219
let Inst{25} = vm;
221220
// Inst{24-20} provided by subclasses
222221
let Inst{19-15} = rs1;
223-
let Inst{14-12} = width;
222+
let Inst{14-12} = width.Value{2-0};
224223
let Inst{11-7} = vs3;
225224
let Inst{6-0} = OPC_STORE_FP.Value;
226225

227226
let Uses = [VL, VTYPE];
228227
}
229228

230-
class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop, bits<3> width, dag outs,
229+
class RVInstVSU<bits<3> nf, RISCVWidth width, RISCVSUMOP sumop, dag outs,
231230
dag ins, string opcodestr, string argstr>
232-
: RVInstVStoreBase<nf, mew, MOPSTUnitStride, width, outs, ins, opcodestr,
231+
: RVInstVStoreBase<nf, width, MOPSTUnitStride, outs, ins, opcodestr,
233232
argstr> {
234233
let Inst{24-20} = sumop.Value;
235234
}
236235

237-
class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
238-
dag outs, dag ins, string opcodestr, string argstr>
239-
: RVInstVStoreBase<nf, mew, MOPSTStrided, width, outs, ins, opcodestr,
236+
class RVInstVSS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
237+
string opcodestr, string argstr>
238+
: RVInstVStoreBase<nf, width, MOPSTStrided, outs, ins, opcodestr,
240239
argstr> {
241240
bits<5> rs2;
242241

243242
let Inst{24-20} = rs2;
244243
}
245244

246-
class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
247-
dag outs, dag ins, string opcodestr, string argstr>
248-
: RVInstVStoreBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
245+
class RVInstVSX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
246+
string opcodestr, string argstr>
247+
: RVInstVStoreBase<nf, width, mop, outs, ins, opcodestr, argstr> {
249248
bits<5> vs2;
250249

251250
let Inst{24-20} = vs2;

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td‎

Lines changed: 23 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -340,15 +340,15 @@ def RISCVBaseVXMemOpTable : GenericTable {
340340
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
341341
// unit-stride load vd, (rs1), vm
342342
class VUnitStrideLoad<RISCVWidth width, string opcodestr>
343-
: RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
343+
: RVInstVLU<0b000, width, LUMOPUnitStride,
344344
(outs VR:$vd),
345345
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
346346

347347
let vm = 1, RVVConstraint = NoConstraint in {
348348
// unit-stride whole register load vl<nf>r.v vd, (rs1)
349349
class VWholeLoad<int lmul, RISCVWidth width, string opcodestr, RegisterClass VRC>
350-
: RVInstVLU<!sub(lmul, 1), width.Value{3}, LUMOPUnitStrideWholeReg,
351-
width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1),
350+
: RVInstVLU<!sub(lmul, 1), width, LUMOPUnitStrideWholeReg, (outs VRC:$vd),
351+
(ins GPRMemZeroOffset:$rs1),
352352
opcodestr, "$vd, $rs1"> {
353353
assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8";
354354

@@ -357,51 +357,44 @@ class VWholeLoad<int lmul, RISCVWidth width, string opcodestr, RegisterClass VRC
357357

358358
// unit-stride mask load vd, (rs1)
359359
class VUnitStrideMaskLoad<string opcodestr>
360-
: RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0},
361-
(outs VR:$vd),
360+
: RVInstVLU<0b000, LSWidth8, LUMOPUnitStrideMask, (outs VR:$vd),
362361
(ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1">;
363362
} // vm = 1, RVVConstraint = NoConstraint
364363

365364
// unit-stride fault-only-first load vd, (rs1), vm
366365
class VUnitStrideLoadFF<RISCVWidth width, string opcodestr>
367-
: RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
368-
(outs VR:$vd),
366+
: RVInstVLU<0b000, width, LUMOPUnitStrideFF, (outs VR:$vd),
369367
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
370368

371369
// strided load vd, (rs1), rs2, vm
372370
class VStridedLoad<RISCVWidth width, string opcodestr>
373-
: RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
374-
(outs VR:$vd),
371+
: RVInstVLS<0b000, width, (outs VR:$vd),
375372
(ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
376373
"$vd, $rs1, $rs2$vm">;
377374

378375
// indexed load vd, (rs1), vs2, vm
379376
class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
380-
: RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
381-
(outs VR:$vd),
377+
: RVInstVLX<0b000, width, mop, (outs VR:$vd),
382378
(ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
383379
"$vd, $rs1, $vs2$vm">;
384380

385381
// unit-stride segment load vd, (rs1), vm
386382
class VUnitStrideSegmentLoad<int nfields, RISCVWidth width, string opcodestr>
387-
: RVInstVLU<!sub(nfields, 1), width.Value{3}, LUMOPUnitStride, width.Value{2-0},
388-
(outs VR:$vd),
383+
: RVInstVLU<!sub(nfields, 1), width, LUMOPUnitStride, (outs VR:$vd),
389384
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm"> {
390385
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
391386
}
392387

393388
// segment fault-only-first load vd, (rs1), vm
394389
class VUnitStrideSegmentLoadFF<int nfields, RISCVWidth width, string opcodestr>
395-
: RVInstVLU<!sub(nfields, 1), width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
396-
(outs VR:$vd),
390+
: RVInstVLU<!sub(nfields, 1), width, LUMOPUnitStrideFF, (outs VR:$vd),
397391
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm"> {
398392
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
399393
}
400394

401395
// strided segment load vd, (rs1), rs2, vm
402396
class VStridedSegmentLoad<int nfields, RISCVWidth width, string opcodestr>
403-
: RVInstVLS<!sub(nfields, 1), width.Value{3}, width.Value{2-0},
404-
(outs VR:$vd),
397+
: RVInstVLS<!sub(nfields, 1), width, (outs VR:$vd),
405398
(ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
406399
"$vd, $rs1, $rs2$vm"> {
407400
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
@@ -410,8 +403,7 @@ class VStridedSegmentLoad<int nfields, RISCVWidth width, string opcodestr>
410403
// indexed segment load vd, (rs1), vs2, vm
411404
class VIndexedSegmentLoad<int nfields, RISCVMOP mop, RISCVWidth width,
412405
string opcodestr>
413-
: RVInstVLX<!sub(nfields, 1), width.Value{3}, mop, width.Value{2-0},
414-
(outs VR:$vd),
406+
: RVInstVLX<!sub(nfields, 1), width, mop, (outs VR:$vd),
415407
(ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
416408
"$vd, $rs1, $vs2$vm"> {
417409
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
@@ -421,15 +413,15 @@ class VIndexedSegmentLoad<int nfields, RISCVMOP mop, RISCVWidth width,
421413
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
422414
// unit-stride store vd, vs3, (rs1), vm
423415
class VUnitStrideStore<RISCVWidth width, string opcodestr>
424-
: RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
425-
(outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
416+
: RVInstVSU<0b000, width, SUMOPUnitStride, (outs),
417+
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
426418
"$vs3, ${rs1}$vm">;
427419

428420
let vm = 1 in {
429421
// vs<lmul>r.v vd, (rs1)
430422
class VWholeStore<int lmul, string opcodestr, RegisterClass VRC>
431-
: RVInstVSU<!sub(lmul, 1), 0, SUMOPUnitStrideWholeReg,
432-
0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
423+
: RVInstVSU<!sub(lmul, 1), LSWidth8, SUMOPUnitStrideWholeReg, (outs),
424+
(ins VRC:$vs3, GPRMemZeroOffset:$rs1),
433425
opcodestr, "$vs3, $rs1"> {
434426
assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8";
435427

@@ -438,34 +430,34 @@ class VWholeStore<int lmul, string opcodestr, RegisterClass VRC>
438430

439431
// unit-stride mask store vd, vs3, (rs1)
440432
class VUnitStrideMaskStore<string opcodestr>
441-
: RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0},
442-
(outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr,
433+
: RVInstVSU<0b000, LSWidth8, SUMOPUnitStrideMask, (outs),
434+
(ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr,
443435
"$vs3, $rs1">;
444436
} // vm = 1
445437

446438
// strided store vd, vs3, (rs1), rs2, vm
447439
class VStridedStore<RISCVWidth width, string opcodestr>
448-
: RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
440+
: RVInstVSS<0b000, width, (outs),
449441
(ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
450442
opcodestr, "$vs3, $rs1, $rs2$vm">;
451443

452444
// indexed store vd, vs3, (rs1), vs2, vm
453445
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
454-
: RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
446+
: RVInstVSX<0b000, width, mop, (outs),
455447
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
456448
opcodestr, "$vs3, $rs1, $vs2$vm">;
457449

458450
// segment store vd, vs3, (rs1), vm
459451
class VUnitStrideSegmentStore<int nfields, RISCVWidth width, string opcodestr>
460-
: RVInstVSU<!sub(nfields, 1), width.Value{3}, SUMOPUnitStride, width.Value{2-0},
461-
(outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
452+
: RVInstVSU<!sub(nfields, 1), width, SUMOPUnitStride, (outs),
453+
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
462454
"$vs3, ${rs1}$vm"> {
463455
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
464456
}
465457

466458
// segment store vd, vs3, (rs1), rs2, vm
467459
class VStridedSegmentStore<int nfields, RISCVWidth width, string opcodestr>
468-
: RVInstVSS<!sub(nfields, 1), width.Value{3}, width.Value{2-0}, (outs),
460+
: RVInstVSS<!sub(nfields, 1), width, (outs),
469461
(ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
470462
opcodestr, "$vs3, $rs1, $rs2$vm"> {
471463
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
@@ -474,7 +466,7 @@ class VStridedSegmentStore<int nfields, RISCVWidth width, string opcodestr>
474466
// segment store vd, vs3, (rs1), vs2, vm
475467
class VIndexedSegmentStore<int nfields, RISCVMOP mop, RISCVWidth width,
476468
string opcodestr>
477-
: RVInstVSX<!sub(nfields, 1), width.Value{3}, mop, width.Value{2-0}, (outs),
469+
: RVInstVSX<!sub(nfields, 1), width, mop, (outs),
478470
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
479471
opcodestr, "$vs3, $rs1, $vs2$vm"> {
480472
assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";

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