Skip to content

Commit cdc633e

Browse files
committed
Revert "TargetLowering: fix an infinite DAG combine in SimplifySETCC"
This reverts commit b76c85b. It broke the RISCV-enabled bots. Oops.
1 parent 4f92557 commit cdc633e

2 files changed

Lines changed: 2 additions & 35 deletions

File tree

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4227,12 +4227,12 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
42274227
bool N1ConstOrSplat =
42284228
isConstOrConstSplat(N1, /*AllowUndefs*/ false, /*AllowTruncate*/ true);
42294229

4230-
// Canonicalize toward having the constant on the RHS.
4230+
// Ensure that the constant occurs on the RHS and fold constant comparisons.
42314231
// TODO: Handle non-splat vector constants. All undef causes trouble.
42324232
// FIXME: We can't yet fold constant scalable vector splats, so avoid an
42334233
// infinite loop here when we encounter one.
42344234
ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
4235-
if (N0ConstOrSplat && !N1ConstOrSplat && !OpVT.isScalableVector() &&
4235+
if (N0ConstOrSplat && (!OpVT.isScalableVector() || !N1ConstOrSplat) &&
42364236
(DCI.isBeforeLegalizeOps() ||
42374237
isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
42384238
return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);

llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll

Lines changed: 0 additions & 33 deletions
This file was deleted.

0 commit comments

Comments
 (0)