|
| 1 | +//! Emulated UART 16550. (ref: https://wiki.osdev.org/Serial_Ports) |
| 2 | +
|
| 3 | +use super::PortIoDevice; |
| 4 | +use crate::arch::uart; |
| 5 | + |
| 6 | +use rvm::{RvmError, RvmResult}; |
| 7 | +use spin::Mutex; |
| 8 | + |
| 9 | +const DATA_REG: u16 = 0; |
| 10 | +const INT_EN_REG: u16 = 1; |
| 11 | +const FIFO_CTRL_REG: u16 = 2; |
| 12 | +const LINE_CTRL_REG: u16 = 3; |
| 13 | +const MODEM_CTRL_REG: u16 = 4; |
| 14 | +const LINE_STATUS_REG: u16 = 5; |
| 15 | +const MODEM_STATUS_REG: u16 = 6; |
| 16 | +const SCRATCH_REG: u16 = 7; |
| 17 | + |
| 18 | +const UART_FIFO_CAPACITY: usize = 16; |
| 19 | + |
| 20 | +bitflags::bitflags! { |
| 21 | + /// Line status flags |
| 22 | + struct LineStsFlags: u8 { |
| 23 | + const INPUT_FULL = 1; |
| 24 | + // 1 to 4 unknown |
| 25 | + const OUTPUT_EMPTY = 1 << 5; |
| 26 | + // 6 and 7 unknown |
| 27 | + } |
| 28 | +} |
| 29 | + |
| 30 | +/// FIFO queue for caching bytes read. |
| 31 | +struct Fifo<const CAP: usize> { |
| 32 | + buf: [u8; CAP], |
| 33 | + head: usize, |
| 34 | + num: usize, |
| 35 | +} |
| 36 | + |
| 37 | +impl<const CAP: usize> Fifo<CAP> { |
| 38 | + const fn new() -> Self { |
| 39 | + Self { |
| 40 | + buf: [0; CAP], |
| 41 | + head: 0, |
| 42 | + num: 0, |
| 43 | + } |
| 44 | + } |
| 45 | + |
| 46 | + fn is_empty(&self) -> bool { |
| 47 | + self.num == 0 |
| 48 | + } |
| 49 | + |
| 50 | + fn is_full(&self) -> bool { |
| 51 | + self.num == CAP |
| 52 | + } |
| 53 | + |
| 54 | + fn push(&mut self, value: u8) { |
| 55 | + assert!(self.num < CAP); |
| 56 | + self.buf[(self.head + self.num) % CAP] = value; |
| 57 | + self.num += 1; |
| 58 | + } |
| 59 | + |
| 60 | + fn pop(&mut self) -> u8 { |
| 61 | + assert!(self.num > 0); |
| 62 | + let ret = self.buf[self.head]; |
| 63 | + self.head += 1; |
| 64 | + self.head %= CAP; |
| 65 | + self.num -= 1; |
| 66 | + ret |
| 67 | + } |
| 68 | +} |
| 69 | + |
| 70 | +pub struct Uart16550 { |
| 71 | + port_base: u16, |
| 72 | + fifo: Mutex<Fifo<UART_FIFO_CAPACITY>>, |
| 73 | +} |
| 74 | + |
| 75 | +impl PortIoDevice for Uart16550 { |
| 76 | + fn port_range(&self) -> core::ops::Range<u16> { |
| 77 | + self.port_base..self.port_base + 8 |
| 78 | + } |
| 79 | + |
| 80 | + fn read(&self, port: u16, access_size: u8) -> RvmResult<u32> { |
| 81 | + if access_size != 1 { |
| 82 | + error!("Invalid serial port I/O read size: {} != 1", access_size); |
| 83 | + return Err(RvmError::InvalidParam); |
| 84 | + } |
| 85 | + let ret = match port - self.port_base { |
| 86 | + DATA_REG => { |
| 87 | + // read a byte from FIFO |
| 88 | + let mut fifo = self.fifo.lock(); |
| 89 | + if fifo.is_empty() { |
| 90 | + 0 |
| 91 | + } else { |
| 92 | + fifo.pop() |
| 93 | + } |
| 94 | + } |
| 95 | + LINE_STATUS_REG => { |
| 96 | + // check if the physical serial port has an available byte, and push it to FIFO. |
| 97 | + let mut fifo = self.fifo.lock(); |
| 98 | + if !fifo.is_full() { |
| 99 | + if let Some(c) = uart::console_getchar() { |
| 100 | + fifo.push(c); |
| 101 | + } |
| 102 | + } |
| 103 | + let mut lsr = LineStsFlags::OUTPUT_EMPTY; |
| 104 | + if !fifo.is_empty() { |
| 105 | + lsr |= LineStsFlags::INPUT_FULL; |
| 106 | + } |
| 107 | + lsr.bits() |
| 108 | + } |
| 109 | + INT_EN_REG | FIFO_CTRL_REG | LINE_CTRL_REG | MODEM_CTRL_REG | MODEM_STATUS_REG |
| 110 | + | SCRATCH_REG => { |
| 111 | + info!("Unimplemented serial port I/O read: {:#x}", port); // unimplemented |
| 112 | + 0 |
| 113 | + } |
| 114 | + _ => unreachable!(), |
| 115 | + }; |
| 116 | + Ok(ret as u32) |
| 117 | + } |
| 118 | + |
| 119 | + fn write(&self, port: u16, access_size: u8, value: u32) -> RvmResult { |
| 120 | + if access_size != 1 { |
| 121 | + error!("Invalid serial port I/O write size: {} != 1", access_size); |
| 122 | + return Err(RvmError::InvalidParam); |
| 123 | + } |
| 124 | + match port - self.port_base { |
| 125 | + DATA_REG => uart::console_putchar(value as u8), |
| 126 | + INT_EN_REG | FIFO_CTRL_REG | LINE_CTRL_REG | MODEM_CTRL_REG | SCRATCH_REG => { |
| 127 | + info!("Unimplemented serial port I/O write: {:#x}", port); // unimplemented |
| 128 | + } |
| 129 | + LINE_STATUS_REG => {} // ignore |
| 130 | + _ => unreachable!(), |
| 131 | + } |
| 132 | + Ok(()) |
| 133 | + } |
| 134 | +} |
| 135 | + |
| 136 | +impl Uart16550 { |
| 137 | + pub const fn new(port_base: u16) -> Self { |
| 138 | + Self { |
| 139 | + port_base, |
| 140 | + fifo: Mutex::new(Fifo::new()), |
| 141 | + } |
| 142 | + } |
| 143 | +} |
0 commit comments