Step 0-2: handle traps, enable APIC timer

Author: equation314

hypervisor/Cargo.lock

@@ -11,7 +11,10 @@ log = "0.4"
 spin = "0.9"
 cfg-if = "1.0"
 bitflags = "1.3"
+lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 x86 = "0.52"
 x86_64 = "0.14"
+x2apic = "0.4"
+raw-cpuid = "10.6"

hypervisor/Cargo.toml

@@ -25,7 +25,7 @@ GDB := gdb-multiarch
 qemu := qemu-system-$(ARCH)
 qemu_args := -nographic -m 128M
 
-qemu_args += -cpu host -accel kvm
+qemu_args += -cpu host,+x2apic -accel kvm
 
 ifeq ($(ARCH), x86_64)
   qemu_args += \

hypervisor/Makefile

@@ -0,0 +1,56 @@
+use x86_64::instructions::tables::{lgdt, load_tss};
+use x86_64::registers::segmentation::{Segment, SegmentSelector, CS};
+use x86_64::structures::gdt::{Descriptor, DescriptorFlags};
+use x86_64::structures::{tss::TaskStateSegment, DescriptorTablePointer};
+use x86_64::{addr::VirtAddr, PrivilegeLevel};
+
+lazy_static::lazy_static! {
+    static ref TSS: TaskStateSegment = TaskStateSegment::new();
+    static ref GDT: GdtStruct = GdtStruct::new(&TSS);
+}
+
+struct GdtStruct {
+    table: [u64; 16],
+}
+
+impl GdtStruct {
+    pub const KCODE_SELECTOR: SegmentSelector = SegmentSelector::new(1, PrivilegeLevel::Ring0);
+    pub const _KDATA_SELECTOR: SegmentSelector = SegmentSelector::new(2, PrivilegeLevel::Ring0);
+    pub const TSS_SELECTOR: SegmentSelector = SegmentSelector::new(3, PrivilegeLevel::Ring0);
+
+    pub fn new(tss: &'static TaskStateSegment) -> Self {
+        let mut table = [0; 16];
+        table[1] = DescriptorFlags::KERNEL_CODE64.bits(); // 0x00af9b000000ffff
+        table[2] = DescriptorFlags::KERNEL_DATA.bits(); // 0x00cf93000000ffff
+        if let Descriptor::SystemSegment(low, high) = Descriptor::tss_segment(tss) {
+            table[3] = low;
+            table[4] = high;
+        }
+        Self { table }
+    }
+
+    fn pointer(&self) -> DescriptorTablePointer {
+        DescriptorTablePointer {
+            base: VirtAddr::new(self.table.as_ptr() as u64),
+            limit: (core::mem::size_of_val(&self.table) - 1) as u16,
+        }
+    }
+
+    pub fn load(&'static self) {
+        unsafe {
+            lgdt(&self.pointer());
+            CS::set_reg(GdtStruct::KCODE_SELECTOR);
+        }
+    }
+
+    pub fn load_tss(&'static self, selector: SegmentSelector) {
+        unsafe { load_tss(selector) };
+    }
+}
+
+pub fn init() {
+    println!("Initializing GDT...");
+    lazy_static::initialize(&GDT);
+    GDT.load();
+    GDT.load_tss(GdtStruct::TSS_SELECTOR);
+}

hypervisor/src/arch/x86_64/gdt.rs

@@ -0,0 +1,44 @@
+use x86_64::structures::idt::{Entry, HandlerFunc, InterruptDescriptorTable};
+
+const NUM_INT: usize = 256;
+
+lazy_static::lazy_static! {
+    static ref IDT: IdtStruct = IdtStruct::new();
+}
+
+struct IdtStruct {
+    table: InterruptDescriptorTable,
+}
+
+impl IdtStruct {
+    fn new() -> Self {
+        extern "C" {
+            #[link_name = "trap_handler_table"]
+            static ENTRIES: [extern "C" fn(); NUM_INT];
+        }
+        let mut idt = Self {
+            table: InterruptDescriptorTable::new(),
+        };
+
+        let entries = unsafe {
+            core::slice::from_raw_parts_mut(
+                &mut idt.table as *mut _ as *mut Entry<HandlerFunc>,
+                NUM_INT,
+            )
+        };
+        for i in 0..NUM_INT {
+            entries[i].set_handler_fn(unsafe { core::mem::transmute(ENTRIES[i]) });
+        }
+        idt
+    }
+
+    fn load(&'static self) {
+        self.table.load();
+    }
+}
+
+pub fn init() {
+    println!("Initializing IDT...");
+    lazy_static::initialize(&IDT);
+    IDT.load();
+}

hypervisor/src/arch/x86_64/idt.rs

@@ -0,0 +1,27 @@
+#![allow(dead_code)]
+
+use core::arch::asm;
+
+use x86_64::registers::{rflags, rflags::RFlags};
+
+#[inline]
+pub fn enable_irqs() {
+    unsafe { asm!("sti") };
+}
+
+#[inline]
+pub fn disable_irqs() {
+    unsafe { asm!("cli") };
+}
+
+#[inline]
+pub fn irqs_disabled() -> bool {
+    !rflags::read().contains(RFlags::INTERRUPT_FLAG)
+}
+
+#[inline]
+pub fn wait_for_ints() {
+    if !irqs_disabled() {
+        x86_64::instructions::hlt();
+    }
+}

hypervisor/src/arch/x86_64/instructions.rs

@@ -0,0 +1,38 @@
+use x2apic::lapic::{LocalApic, LocalApicBuilder};
+use x86_64::instructions::port::Port;
+
+use self::vectors::*;
+
+pub mod vectors {
+    pub const APIC_TIMER_VECTOR: u8 = 0xf0;
+    pub const APIC_SPURIOUS_VECTOR: u8 = 0xf1;
+    pub const APIC_ERROR_VECTOR: u8 = 0xf2;
+}
+
+static mut LOCAL_APIC: Option<LocalApic> = None;
+
+pub fn local_apic<'a>() -> &'a mut LocalApic {
+    // It's safe as LAPIC is per-cpu.
+    unsafe { LOCAL_APIC.as_mut().unwrap() }
+}
+
+pub fn init() {
+    println!("Initializing Local APIC...");
+
+    unsafe {
+        // Disable 8259A interrupt controllers
+        Port::<u8>::new(0x20).write(0xff);
+        Port::<u8>::new(0xA0).write(0xff);
+    }
+
+    let mut lapic = LocalApicBuilder::new()
+        .timer_vector(APIC_TIMER_VECTOR as _)
+        .error_vector(APIC_ERROR_VECTOR as _)
+        .spurious_vector(APIC_SPURIOUS_VECTOR as _)
+        .build()
+        .unwrap();
+    unsafe {
+        lapic.enable();
+        LOCAL_APIC = Some(lapic);
+    }
+}

hypervisor/src/arch/x86_64/lapic.rs

@@ -1,9 +1,23 @@
 mod boot;
+mod gdt;
+mod idt;
+mod lapic;
+mod trap;
 
+pub mod instructions;
+pub mod timer;
 pub mod uart16550;
 
+pub use trap::handle_irq;
 pub use uart16550 as uart;
 
 pub fn init_early() {
     uart::init();
 }
+
+pub fn init() {
+    gdt::init();
+    idt::init();
+    lapic::init();
+    timer::init();
+}

hypervisor/src/arch/x86_64/mod.rs

@@ -0,0 +1,37 @@
+use raw_cpuid::CpuId;
+use x2apic::lapic::{TimerDivide, TimerMode};
+
+use crate::config::TICKS_PER_SEC;
+
+use super::lapic::local_apic;
+
+const LAPIC_TICKS_PER_SEC: u64 = 1_000_000_000; // TODO: need to calibrate
+
+static mut CPU_FREQ_MHZ: u64 = 4_000;
+
+pub fn current_ticks() -> u64 {
+    unsafe { core::arch::x86_64::_rdtsc() }
+}
+
+pub fn ticks_to_nanos(ticks: u64) -> u64 {
+    ticks * 1_000 / unsafe { CPU_FREQ_MHZ }
+}
+
+pub fn init() {
+    if let Some(freq) = CpuId::new()
+        .get_processor_frequency_info()
+        .map(|info| info.processor_base_frequency())
+    {
+        if freq > 0 {
+            println!("Got TSC frequency by CPUID: {} MHz", freq);
+            unsafe { CPU_FREQ_MHZ = freq as u64 }
+        }
+    }
+
+    let lapic = local_apic();
+    unsafe {
+        lapic.set_timer_mode(TimerMode::Periodic);
+        lapic.set_timer_divide(TimerDivide::Div256); // indeed it is Div1, the name is confusing.
+        lapic.set_timer_initial((LAPIC_TICKS_PER_SEC / TICKS_PER_SEC) as u32);
+    }
+}