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dts: mt7987: merge netsys dtsi
1 parent cf38a86 commit 7a66ea9

2 files changed

Lines changed: 132 additions & 125 deletions

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‎arch/arm64/boot/dts/mediatek/mt7987-netsys.dtsi‎

Lines changed: 0 additions & 124 deletions
This file was deleted.

‎arch/arm64/boot/dts/mediatek/mt7987a.dtsi‎

Lines changed: 132 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,15 @@
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/dts-v1/;
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/clock/mediatek,mt7987-clk.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include "mt7987.dtsi"
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#include "mt7987-pinctrl.dtsi"
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#include "mt7987-netsys.dtsi"
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/ {
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compatible = "mediatek,mt7987a", "mediatek,mt7987";
@@ -36,6 +42,131 @@
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status = "okay";
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};
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&netsys {
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ethwarp: syscon@15031000 {
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compatible = "mediatek,mt7988-ethwarp", "syscon";
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reg = <0 0x15031000 0 0x1000>;
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#clock-cells = <1>;
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};
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eth_sram: sram@15400000 {
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compatible = "mmio-sram";
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reg = <0 0x15400000 0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x15400000 0 0x20000>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7987-eth";
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reg = <0 0x15100000 0 0x80000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "fe0","fe1","fe2","fe3",
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"pdma0","pdma1","pdma2","pdma3";
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clocks = <&ethsys CLK_ETHDMA_FE_EN>,
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<&ethsys CLK_ETHDMA_GP2_EN>,
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<&ethsys CLK_ETHDMA_GP1_EN>,
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<&ethsys CLK_ETHDMA_GP3_EN>,
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<&topckgen CLK_TOP_ETH_GMII_SEL>,
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<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
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<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
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<&topckgen CLK_TOP_ETH_SYS_SEL>,
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<&topckgen CLK_TOP_ETH_XGMII_SEL>,
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<&topckgen CLK_TOP_ETH_MII_SEL>,
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<&topckgen CLK_TOP_NETSYS_SEL>,
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<&topckgen CLK_TOP_NETSYS_500M_SEL>,
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<&topckgen CLK_TOP_NETSYS_2X_SEL>;
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clock-names = "fe", "gp2", "gp1", "gp3",
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"top_eth_gmii_sel", "top_eth_refck_50m_sel",
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"top_eth_sys_200m_sel", "top_eth_sys_sel",
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"top_eth_xgmii_sel", "top_eth_mii_sel",
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"top_netsys_sel", "top_netsys_500m_sel",
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"top_netsys_pao_2x_sel";
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assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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<&topckgen CLK_TOP_SGM_0_SEL>,
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<&topckgen CLK_TOP_SGM_1_SEL>;
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assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
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<&apmixedsys CLK_APMIXED_SGMPLL>,
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<&apmixedsys CLK_APMIXED_SGMPLL>;
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mediatek,ethsys = <&ethsys>;
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mediatek,infracfg = <&topmisc>;
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pinctrl-names = "default";
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pinctrl-0 = <&mdio0_pins>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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sram = <&eth_sram>;
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status = "disabled";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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pcs-handle = <&sgmiipcs0>;
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status = "disabled";
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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status = "disabled";
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};
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gmac2: mac@2 {
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compatible = "mediatek,eth-mac";
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reg = <2>;
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pcs-handle = <&sgmiipcs1>;
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status = "disabled";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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hnat: hnat@15000000 {
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compatible = "mediatek,mtk-hnat_v5";
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reg = <0 0x15100000 0 0x80000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ethsys 0>;
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reset-names = "mtketh";
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status = "disabled";
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};
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crypto: crypto@15600000 {
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compatible = "inside-secure,safexcel-eip197b",
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"security-ip-197-srv";
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reg = <0 0x15600000 0 0x180000>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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eth = <&eth>;
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status = "disabled";
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};
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};
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&crypto {
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status = "okay";
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};
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&eth {
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status = "okay";
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};
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&hnat {
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mtketh-wan = "eth1";
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mtketh-lan = "lan";
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mtketh-max-gmac = <2>;
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mtketh-ppe-num = <1>;
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;

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