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feephfeeph
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test: improve code coverage (#29)
2 parents bf524a6 + 02ecadf commit d774e4d

3 files changed

Lines changed: 120 additions & 6 deletions

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‎feeph/i2cmux/generic.py‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,8 @@ def __init__(self, i2c_bus: busio.I2C, i2c_adr: int, tca_adr: int, tca_cid: int,
4343
# this a low-level class and should not be used directly
4444
# specific implementations should be derive from this class and
4545
# they are expected to perform all necessary input validation
46-
self._i2c_bus = i2c_bus
47-
self._i2c_adr = i2c_adr
46+
super().__init__(i2c_bus=i2c_bus, i2c_adr=i2c_adr)
47+
self._channel_switch = bytearray()
4848
self._tca_adr = tca_adr
4949
self._tca_cid = tca_cid
5050
self._timeout_ms = timeout_ms
@@ -79,8 +79,8 @@ def __enter__(self) -> BurstHandle:
7979
# successfully acquired a lock
8080
# -----------------------------------------------------------------
8181
# send I²C command to configure the correct channel
82-
self.channel_switch = bytearray([1 << self._tca_cid])
83-
self._i2c_bus.writeto(self._tca_adr, self.channel_switch)
82+
self._channel_switch = bytearray([1 << self._tca_cid])
83+
self._i2c_bus.writeto(self._tca_adr, self._channel_switch)
8484
# -----------------------------------------------------------------
8585
elapsed_ns = time.perf_counter_ns() - self._timestart_ns
8686
LH.debug("[%d] Acquired a lock on the I²C bus after %d ms.", id(self), elapsed_ns / (1000 * 1000))

‎tests/test_tca9546a.py‎

Lines changed: 58 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121

2222
import feeph.i2cmux as sut
2323

24-
2524
if os.environ.get('TEST_TCA9546A_CHIP', 'n') == 'y':
2625
HAS_HARDWARE = True
2726
else:
@@ -84,3 +83,61 @@ def test_multiplexed_device(self):
8483
computed = bh.read_register(0x01)
8584
expected = 0x12
8685
self.assertEqual(computed, expected)
86+
87+
# ---------------------------------------------------------------------
88+
89+
def test_invalid_device_address(self):
90+
# this code tests the equivalent of:
91+
# with sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0xFFFF) as bh:
92+
# ...
93+
i2c_bus = EmulatedI2C(state={})
94+
# -----------------------------------------------------------------
95+
# -----------------------------------------------------------------
96+
self.assertRaises(ValueError, sut.TCA9546A, i2c_bus=i2c_bus, i2c_adr=0xFFFF)
97+
98+
def test_invalid_tca_address(self):
99+
# this code tests the equivalent of:
100+
# with sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0x4C, tca_adr=0x07) as bh:
101+
# ...
102+
i2c_bus = EmulatedI2C(state={})
103+
# -----------------------------------------------------------------
104+
# -----------------------------------------------------------------
105+
self.assertRaises(ValueError, sut.TCA9546A, i2c_bus=i2c_bus, i2c_adr=0x4C, tca_adr=0x07)
106+
107+
def test_invalid_timeout(self):
108+
# this code tests the equivalent of:
109+
# with sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=0) as bh:
110+
# ...
111+
i2c_bus = EmulatedI2C(state={}, lock_chance=1)
112+
# -----------------------------------------------------------------
113+
# -----------------------------------------------------------------
114+
self.assertRaises(ValueError, sut.TCA9546A, i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=0)
115+
116+
def test_hard_to_lock(self):
117+
state = {
118+
0x70: {
119+
-1: 0x00,
120+
},
121+
0x4C: {
122+
0x00: 0x12,
123+
},
124+
}
125+
i2c_bus = EmulatedI2C(state=state, lock_chance=1)
126+
# -----------------------------------------------------------------
127+
# simulating an extremely busy I²C bus
128+
# (there's a 1 percent chance to successfully lock the bus)
129+
with sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=None) as bh:
130+
computed = bh.read_register(0x00)
131+
expected = 0x12
132+
# -----------------------------------------------------------------
133+
self.assertEqual(computed, expected)
134+
135+
def test_unable_to_lock(self):
136+
# this code tests the equivalent of:
137+
# with sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0x4C) as bh:
138+
# ...
139+
i2c_bus = EmulatedI2C(state={}, lock_chance=0) # impossible to acquire a lock
140+
bh = sut.TCA9546A(i2c_bus=i2c_bus, i2c_adr=0x4C)
141+
# -----------------------------------------------------------------
142+
# -----------------------------------------------------------------
143+
self.assertRaises(RuntimeError, bh.__enter__)

‎tests/test_tca9548a.py‎

Lines changed: 58 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818

1919
import feeph.i2cmux as sut
2020

21-
2221
if os.environ.get('TEST_TCA9548A_CHIP', 'n') == 'y':
2322
HAS_HARDWARE = True
2423
else:
@@ -80,3 +79,61 @@ def test_multiplexed_device(self):
8079
computed = bh.read_register(0x01)
8180
expected = 0x12
8281
self.assertEqual(computed, expected)
82+
83+
# ---------------------------------------------------------------------
84+
85+
def test_invalid_device_address(self):
86+
# this code tests the equivalent of:
87+
# with sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0xFFFF) as bh:
88+
# ...
89+
i2c_bus = EmulatedI2C(state={})
90+
# -----------------------------------------------------------------
91+
# -----------------------------------------------------------------
92+
self.assertRaises(ValueError, sut.TCA9548A, i2c_bus=i2c_bus, i2c_adr=0xFFFF)
93+
94+
def test_invalid_tca_address(self):
95+
# this code tests the equivalent of:
96+
# with sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0x4C, tca_adr=0x07) as bh:
97+
# ...
98+
i2c_bus = EmulatedI2C(state={})
99+
# -----------------------------------------------------------------
100+
# -----------------------------------------------------------------
101+
self.assertRaises(ValueError, sut.TCA9548A, i2c_bus=i2c_bus, i2c_adr=0x4C, tca_adr=0x07)
102+
103+
def test_invalid_timeout(self):
104+
# this code tests the equivalent of:
105+
# with sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=0) as bh:
106+
# ...
107+
i2c_bus = EmulatedI2C(state={}, lock_chance=1)
108+
# -----------------------------------------------------------------
109+
# -----------------------------------------------------------------
110+
self.assertRaises(ValueError, sut.TCA9548A, i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=0)
111+
112+
def test_hard_to_lock(self):
113+
state = {
114+
0x70: {
115+
-1: 0x00,
116+
},
117+
0x4C: {
118+
0x00: 0x12,
119+
},
120+
}
121+
i2c_bus = EmulatedI2C(state=state, lock_chance=1)
122+
# -----------------------------------------------------------------
123+
# simulating an extremely busy I²C bus
124+
# (there's a 1 percent chance to successfully lock the bus)
125+
with sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0x4C, timeout_ms=None) as bh:
126+
computed = bh.read_register(0x00)
127+
expected = 0x12
128+
# -----------------------------------------------------------------
129+
self.assertEqual(computed, expected)
130+
131+
def test_unable_to_lock(self):
132+
# this code tests the equivalent of:
133+
# with sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0x4C) as bh:
134+
# ...
135+
i2c_bus = EmulatedI2C(state={}, lock_chance=0) # impossible to acquire a lock
136+
bh = sut.TCA9548A(i2c_bus=i2c_bus, i2c_adr=0x4C)
137+
# -----------------------------------------------------------------
138+
# -----------------------------------------------------------------
139+
self.assertRaises(RuntimeError, bh.__enter__)

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