dts64: mt7987: reorder IRQs (FE first) and add irq names

Author: frank-w

arch/arm64/boot/dts/mediatek/mt7987-netsys.dtsi

@@ -21,14 +21,16 @@
 	eth: ethernet@15100000 {
 		compatible = "mediatek,mt7987-eth";
 		reg = <0 0x15100000 0 0x80000>;
-		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "fe0","fe1","fe2","fe3",
+				  "pdma0","pdma1","pdma2","pdma3";
 		clocks = <&ethsys CLK_ETHDMA_FE_EN>,
 			 <&ethsys CLK_ETHDMA_GP2_EN>,
 			 <&ethsys CLK_ETHDMA_GP1_EN>,

arch/arm64/boot/dts/mediatek/mt7987.dtsi

@@ -167,6 +167,7 @@
 					 <&sgmiisys0 CLK_SGM0_TX_EN>,
 					 <&sgmiisys0 CLK_SGM0_RX_EN>;
 				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+				#pcs-cells = <0>;
 			};
 		};
 		sgmiisys1: syscon@10070000 {
@@ -184,6 +185,7 @@
 					 <&sgmiisys1 CLK_SGM1_TX_EN>,
 					 <&sgmiisys1 CLK_SGM1_RX_EN>;
 				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+				#pcs-cells = <0>;
 			};
 		};
 		mcusys: mcusys@10400000 {