|
3 | 3 | / { |
4 | 4 | model = "Bananapi BPI-R4"; |
5 | 5 | compatible = "bananapi,bpi-r4-pro-8x", |
| 6 | + "bananapi,bpi-r4-pro", |
6 | 7 | "mediatek,mt7988a"; |
7 | 8 | }; |
8 | | -//not checked changes: |
9 | | -// 2,3, |
| 9 | + |
10 | 10 | ð { |
11 | 11 | mux: mux-bus { |
12 | 12 | #address-cells = <1>; |
13 | 13 | #size-cells = <0>; |
14 | 14 | mux1: ethernet-mux@1 { |
15 | 15 | compatible = "mediatek,eth-mux"; |
16 | | - reg = <1>; |
| 16 | + reg = <1>; //map to gmac1 |
17 | 17 | chan-sel-gpios = <&pio 3 GPIO_ACTIVE_HIGH>; |
18 | 18 | mod-def0-gpios = <&pio 1 GPIO_ACTIVE_LOW>; //also moddef0 of sfp2 |
19 | 19 | sfp-present-channel = <1>; |
20 | 20 | #address-cells = <1>; |
21 | 21 | #size-cells = <0>; |
| 22 | + |
22 | 23 | channel_10: channel@0 { |
23 | 24 | reg = <0>; |
24 | 25 | phy-mode = "10gbase-r"; |
25 | 26 | phy-connection-type = "10gbase-r"; |
26 | 27 | phy-handle = <&phy28>; |
27 | 28 | }; |
| 29 | + |
28 | 30 | channel_11: channel@1 { |
29 | 31 | reg = <1>; |
30 | 32 | phy-mode = "10gbase-r"; |
|
33 | 35 | sfp = <&sfp2>; |
34 | 36 | }; |
35 | 37 | }; |
36 | | - /*mux2: ethernet-mux@2 { |
37 | | - compatible = "mediatek,eth-mux"; |
38 | | - reg = <2>; |
39 | | - chan-sel-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; |
40 | | - mod-def0-gpios = <&pio 4 GPIO_ACTIVE_LOW>; |
41 | | - sfp-present-channel = <0>; |
42 | | - #address-cells = <1>; |
43 | | - #size-cells = <0>; |
44 | | - channel_20: channel@0 { |
45 | | - reg = <0>; |
46 | | - phy-mode = "10gbase-r"; |
47 | | - phy-connection-type = "10gbase-r"; |
48 | | - managed = "in-band-status"; |
49 | | - sfp = <&sfp1>; |
50 | | - }; |
51 | | - channel_21: channel@1 { |
52 | | - reg = <1>; |
53 | | - phy-mode = "usxgmii"; |
54 | | - phy-connection-type = "usxgmii"; |
55 | | - phy-handle = <&phy24>; |
56 | | - }; |
57 | | - };*/ |
58 | 38 | }; |
59 | 39 | }; |
60 | 40 |
|
61 | 41 | &gmac1 { |
62 | | - phy-mode = "10gbase-r"; |
63 | | - phy-connection-type = "10gbase-r"; |
64 | | - phy = <&phy28>; |
| 42 | + phy-mode = "usxgmii"; |
| 43 | + phy-connection-type = "usxgmii"; |
| 44 | + phy-handle = <&phy28>; |
65 | 45 | status = "okay"; |
66 | 46 | }; |
67 | 47 |
|
68 | 48 | &mdio_bus { |
69 | | - clock-frequency = <12500000>; //for faster fw download to 10G phys |
| 49 | + /* external Airoha AN8831X connected to MXL switch */ |
70 | 50 |
|
71 | | - /* external Airoha AN8831X is connected to Mxl 2.5G switch */ |
72 | 51 | phy24: ethernet-phy@24 { |
73 | 52 | reg = <24>; |
74 | 53 | compatible = "ethernet-phy-ieee802.3-c45"; |
75 | | - //reset-gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; |
76 | 54 | reset-gpios = <&pio 83 GPIO_ACTIVE_LOW>; //change 5 |
77 | 55 | reset-assert-us = <200000>; |
78 | 56 | reset-deassert-us = <350000>; |
|
82 | 60 | #address-cells = <1>; |
83 | 61 | #size-cells = <0>; |
84 | 62 |
|
85 | | - phy24_led0: an8831x_phy24_led0@0 { |
| 63 | + phy24_led0: led@0 { |
86 | 64 | reg = <0>; |
87 | 65 | linux,default-trigger = "netdev"; |
88 | 66 | active-high; |
89 | 67 | status = "okay"; |
90 | 68 | }; |
91 | 69 |
|
92 | | - phy24_led1: an8831x_phy24_led1@1 { |
| 70 | + phy24_led1: led@1 { |
93 | 71 | reg = <1>; |
94 | 72 | linux,default-trigger = "netdev"; |
95 | 73 | active-high; |
|
102 | 80 | phy28: ethernet-phy@28 { |
103 | 81 | reg = <28>; |
104 | 82 | compatible = "ethernet-phy-ieee802.3-c45"; |
105 | | - //reset-gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; |
106 | | - reset-gpios = <&pio 82 GPIO_ACTIVE_LOW>; //change 5 |
| 83 | + reset-gpios = <&pio 82 GPIO_ACTIVE_LOW>; |
107 | 84 | reset-assert-us = <200000>; |
108 | 85 | reset-deassert-us = <350000>; |
109 | 86 | firmware-name = "aeonsemi/as21x1x_fw.bin"; |
|
112 | 89 | #address-cells = <1>; |
113 | 90 | #size-cells = <0>; |
114 | 91 |
|
115 | | - phy28_led0: an8831x_phy28_led0@0 { |
| 92 | + phy28_led0: led@0 { |
116 | 93 | reg = <0>; |
117 | 94 | linux,default-trigger = "netdev"; |
118 | 95 | active-high; |
119 | 96 | status = "okay"; |
120 | 97 | }; |
121 | 98 |
|
122 | | - phy28_led1: an8831x_phy28_led1@1 { |
| 99 | + phy28_led1: led@1 { |
123 | 100 | reg = <1>; |
124 | 101 | linux,default-trigger = "netdev"; |
125 | 102 | active-high; |
|
130 | 107 | }; |
131 | 108 |
|
132 | 109 | &switch16 { |
133 | | - /*ds_mux: ds-mux-bus { |
| 110 | + ds_mux: ds-mux-bus { |
| 111 | + #address-cells = <1>; |
| 112 | + #size-cells = <0>; |
| 113 | + |
134 | 114 | ds_mux0: ds-mux@0 { |
135 | 115 | compatible = "mxl862xx,ds-mux"; |
136 | 116 | reg = <12>; |
137 | 117 | chan-sel-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; |
138 | 118 | mod-def0-gpios = <&pio 4 GPIO_ACTIVE_LOW>; |
139 | 119 | sfp-present-channel = <0>; |
| 120 | + #address-cells = <1>; |
| 121 | + #size-cells = <0>; |
140 | 122 |
|
141 | 123 | ds_channel_0: channel@0 { |
142 | 124 | reg = <0>; |
143 | | - phy-mode = "10gbase-r"; |
144 | | - phy-connection-type = "10gbase-r"; |
| 125 | + phy-mode = "usxgmii"; |
| 126 | + phy-connection-type = "usxgmii"; |
145 | 127 | managed = "in-band-status"; |
146 | 128 | sfp = <&sfp1>; |
147 | 129 | }; |
|
153 | 135 | phy-handle = <&phy24>; |
154 | 136 | }; |
155 | 137 | }; |
156 | | - };*/ |
157 | | - |
| 138 | + }; |
158 | 139 | ports { |
159 | | - /*port6: port@6 { |
| 140 | + port6: port@6 { |
160 | 141 | reg = <12>; |
161 | 142 | label = "mxl_lan5"; |
162 | 143 | phy-mode = "usxgmii"; |
|
167 | 148 | speed = <10000>; |
168 | 149 | full-duplex; |
169 | 150 | }; |
170 | | - };*/ |
| 151 | + }; |
171 | 152 |
|
172 | 153 | }; |
173 | 154 | }; |
0 commit comments