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Mason Changgregkh
Mason Chang
authored and
gregkh
committed
thermal/drivers/mediatek/lvts_thermal: Add lvts commands and their sizes to driver data
commit 6203a5e upstream. Add LVTS commands and their sizes to driver data in preparation for adding different commands. Signed-off-by: Mason Chang <mason-cw.chang@mediatek.com> Link: https://lore.kernel.org/r/20250526102659.30225-3-mason-cw.chang@mediatek.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent d1f4b09 commit 739229e

1 file changed

Lines changed: 52 additions & 13 deletions

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‎drivers/thermal/mediatek/lvts_thermal.c‎

Lines changed: 52 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -92,17 +92,6 @@
9292

9393
#define LVTS_MINIMUM_THRESHOLD 20000
9494

95-
static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
96-
/*
97-
* Write device mask: 0xC1030000
98-
*/
99-
static const u32 default_init_cmds[] = {
100-
0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
101-
0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
102-
0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
103-
0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
104-
};
105-
10695
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
10796
static int golden_temp_offset;
10897

@@ -132,7 +121,11 @@ struct lvts_ctrl_data {
132121

133122
struct lvts_data {
134123
const struct lvts_ctrl_data *lvts_ctrl;
124+
const u32 *conn_cmd;
125+
const u32 *init_cmd;
135126
int num_lvts_ctrl;
127+
int num_conn_cmd;
128+
int num_init_cmd;
136129
int temp_factor;
137130
int temp_offset;
138131
int gt_calib_bit_offset;
@@ -974,9 +967,10 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
974967

975968
static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
976969
{
970+
const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
977971
u32 id;
978972

979-
lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds));
973+
lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd);
980974

981975
/*
982976
* LVTS_ID : Get ID and status of the thermal controller
@@ -995,7 +989,9 @@ static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
995989

996990
static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
997991
{
998-
lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds));
992+
const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
993+
994+
lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd);
999995

1000996
return 0;
1001997
}
@@ -1424,6 +1420,17 @@ static int lvts_resume(struct device *dev)
14241420
return 0;
14251421
}
14261422

1423+
static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
1424+
/*
1425+
* Write device mask: 0xC1030000
1426+
*/
1427+
static const u32 default_init_cmds[] = {
1428+
0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
1429+
0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
1430+
0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
1431+
0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
1432+
};
1433+
14271434
/*
14281435
* The MT8186 calibration data is stored as packed 3-byte little-endian
14291436
* values using a weird layout that makes sense only when viewed as a 32-bit
@@ -1718,15 +1725,23 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
17181725

17191726
static const struct lvts_data mt7988_lvts_ap_data = {
17201727
.lvts_ctrl = mt7988_lvts_ap_data_ctrl,
1728+
.conn_cmd = default_conn_cmds,
1729+
.init_cmd = default_init_cmds,
17211730
.num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
1731+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1732+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17221733
.temp_factor = LVTS_COEFF_A_MT7988,
17231734
.temp_offset = LVTS_COEFF_B_MT7988,
17241735
.gt_calib_bit_offset = 24,
17251736
};
17261737

17271738
static const struct lvts_data mt8186_lvts_data = {
17281739
.lvts_ctrl = mt8186_lvts_data_ctrl,
1740+
.conn_cmd = default_conn_cmds,
1741+
.init_cmd = default_init_cmds,
17291742
.num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
1743+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1744+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17301745
.temp_factor = LVTS_COEFF_A_MT7988,
17311746
.temp_offset = LVTS_COEFF_B_MT7988,
17321747
.gt_calib_bit_offset = 24,
@@ -1735,7 +1750,11 @@ static const struct lvts_data mt8186_lvts_data = {
17351750

17361751
static const struct lvts_data mt8188_lvts_mcu_data = {
17371752
.lvts_ctrl = mt8188_lvts_mcu_data_ctrl,
1753+
.conn_cmd = default_conn_cmds,
1754+
.init_cmd = default_init_cmds,
17381755
.num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
1756+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1757+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17391758
.temp_factor = LVTS_COEFF_A_MT8195,
17401759
.temp_offset = LVTS_COEFF_B_MT8195,
17411760
.gt_calib_bit_offset = 20,
@@ -1744,7 +1763,11 @@ static const struct lvts_data mt8188_lvts_mcu_data = {
17441763

17451764
static const struct lvts_data mt8188_lvts_ap_data = {
17461765
.lvts_ctrl = mt8188_lvts_ap_data_ctrl,
1766+
.conn_cmd = default_conn_cmds,
1767+
.init_cmd = default_init_cmds,
17471768
.num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
1769+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1770+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17481771
.temp_factor = LVTS_COEFF_A_MT8195,
17491772
.temp_offset = LVTS_COEFF_B_MT8195,
17501773
.gt_calib_bit_offset = 20,
@@ -1753,7 +1776,11 @@ static const struct lvts_data mt8188_lvts_ap_data = {
17531776

17541777
static const struct lvts_data mt8192_lvts_mcu_data = {
17551778
.lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
1779+
.conn_cmd = default_conn_cmds,
1780+
.init_cmd = default_init_cmds,
17561781
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
1782+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1783+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17571784
.temp_factor = LVTS_COEFF_A_MT8195,
17581785
.temp_offset = LVTS_COEFF_B_MT8195,
17591786
.gt_calib_bit_offset = 24,
@@ -1762,7 +1789,11 @@ static const struct lvts_data mt8192_lvts_mcu_data = {
17621789

17631790
static const struct lvts_data mt8192_lvts_ap_data = {
17641791
.lvts_ctrl = mt8192_lvts_ap_data_ctrl,
1792+
.conn_cmd = default_conn_cmds,
1793+
.init_cmd = default_init_cmds,
17651794
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
1795+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1796+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17661797
.temp_factor = LVTS_COEFF_A_MT8195,
17671798
.temp_offset = LVTS_COEFF_B_MT8195,
17681799
.gt_calib_bit_offset = 24,
@@ -1771,7 +1802,11 @@ static const struct lvts_data mt8192_lvts_ap_data = {
17711802

17721803
static const struct lvts_data mt8195_lvts_mcu_data = {
17731804
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1805+
.conn_cmd = default_conn_cmds,
1806+
.init_cmd = default_init_cmds,
17741807
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1808+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1809+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17751810
.temp_factor = LVTS_COEFF_A_MT8195,
17761811
.temp_offset = LVTS_COEFF_B_MT8195,
17771812
.gt_calib_bit_offset = 24,
@@ -1780,7 +1815,11 @@ static const struct lvts_data mt8195_lvts_mcu_data = {
17801815

17811816
static const struct lvts_data mt8195_lvts_ap_data = {
17821817
.lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1818+
.conn_cmd = default_conn_cmds,
1819+
.init_cmd = default_init_cmds,
17831820
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1821+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1822+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17841823
.temp_factor = LVTS_COEFF_A_MT8195,
17851824
.temp_offset = LVTS_COEFF_B_MT8195,
17861825
.gt_calib_bit_offset = 24,

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