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bcchen28411frank-w
bcchen28411
authored and
frank-w
committed
net: ethernet: mtk_eth_soc: add mt7987 support
Without this patch, users are unable to bring up ETH driver on the mt7987. Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
1 parent 7026533 commit 7fbf92c

3 files changed

Lines changed: 177 additions & 42 deletions

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‎drivers/net/ethernet/mediatek/mtk_eth_path.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -106,13 +106,14 @@ static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)
106106
return 0;
107107
}
108108

109-
static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
109+
static int set_mux_u3_gmac23_to_qphy(struct mtk_eth *eth, u64 path)
110110
{
111111
unsigned int val = 0, mask = 0, reg = 0;
112112
bool updated = true;
113113

114114
switch (path) {
115115
case MTK_ETH_PATH_GMAC2_SGMII:
116+
case MTK_ETH_PATH_GMAC3_SGMII:
116117
if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
117118
reg = USB_PHY_SWITCH_REG;
118119
val = SGMII_QPHY_SEL;
@@ -283,9 +284,9 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
283284
.cap_bit = MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY,
284285
.set_path = set_mux_gmac2_gmac0_to_gephy,
285286
}, {
286-
.name = "mux_u3_gmac2_to_qphy",
287-
.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
288-
.set_path = set_mux_u3_gmac2_to_qphy,
287+
.name = "mux_u3_gmac23_to_qphy",
288+
.cap_bit = MTK_ETH_MUX_U3_GMAC23_TO_QPHY,
289+
.set_path = set_mux_u3_gmac23_to_qphy,
289290
}, {
290291
.name = "mux_gmac2_to_2p5gphy",
291292
.cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,

‎drivers/net/ethernet/mediatek/mtk_eth_soc.c‎

Lines changed: 115 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -553,9 +553,14 @@ static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
553553
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE,
554554
XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
555555

556-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) |
557-
MTK_XGMAC_FORCE_LINK(mac->id),
558-
MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id));
556+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2))
557+
mtk_m32(mac->hw, XMAC_FORCE_RX_FC_MODE | XMAC_FORCE_TX_FC_MODE |
558+
XMAC_FORCE_LINK_MODE | XMAC_FORCE_LINK,
559+
XMAC_FORCE_RX_FC_MODE | XMAC_FORCE_TX_FC_MODE |
560+
XMAC_FORCE_LINK_MODE, MTK_XMAC_STS_FRC(mac->id));
561+
else
562+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) | MTK_XGMAC_FORCE_LINK(mac->id),
563+
MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id));
559564
}
560565

561566
return 0;
@@ -755,6 +760,7 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
755760
{
756761
struct mtk_mac *mac = container_of(config, struct mtk_mac,
757762
phylink_config);
763+
struct mtk_eth *eth = mac->hw;
758764

759765
if (!mtk_interface_mode_is_xgmii(mac->hw, interface)) {
760766
/* GMAC modes */
@@ -764,12 +770,14 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
764770
if (mtk_is_netsys_v3_or_greater(mac->hw))
765771
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
766772
MTK_XGMAC_STS(mac->id));
767-
} else if (mac->id != MTK_GMAC1_ID) {
773+
} else if (mtk_is_netsys_v3_or_greater(mac->hw) && mac->id != MTK_GMAC1_ID) {
768774
/* XGMAC except for built-in switch */
769775
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE,
770776
MTK_XMAC_MCR(mac->id));
771-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
772-
MTK_XGMAC_STS(mac->id));
777+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2))
778+
mtk_m32(mac->hw, XMAC_FORCE_LINK, 0, MTK_XMAC_STS_FRC(mac->id));
779+
else
780+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
773781
}
774782
}
775783

@@ -783,10 +791,16 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
783791
return;
784792

785793
val = MTK_QTX_SCH_MIN_RATE_EN |
786-
/* minimum: 10 Mbps */
787-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
788-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
789794
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
795+
/* minimum: 10 Mbps */
796+
if (mtk_is_netsys_v3_or_greater(eth) &&
797+
(eth->soc->caps != MT7988_CAPS)) {
798+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
799+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
800+
} else {
801+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
802+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
803+
}
790804
if (mtk_is_netsys_v1(eth))
791805
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
792806

@@ -813,6 +827,30 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
813827
default:
814828
break;
815829
}
830+
} else if (mtk_is_netsys_v3_or_greater(eth) &&
831+
(eth->soc->caps != MT7988_CAPS)) {
832+
switch (speed) {
833+
case SPEED_10:
834+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
835+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
836+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 4) |
837+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
838+
break;
839+
case SPEED_100:
840+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
841+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
842+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 5) |
843+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
844+
break;
845+
case SPEED_1000:
846+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
847+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
848+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 6) |
849+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 10);
850+
break;
851+
default:
852+
break;
853+
}
816854
} else {
817855
switch (speed) {
818856
case SPEED_10:
@@ -887,6 +925,7 @@ static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
887925
int speed, int duplex, bool tx_pause,
888926
bool rx_pause)
889927
{
928+
struct mtk_eth *eth = mac->hw;
890929
u32 mcr;
891930

892931
if (mac->id == MTK_GMAC1_ID)
@@ -898,21 +937,35 @@ static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
898937
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
899938
MTK_XMAC_CNT_CTRL(mac->id));
900939

901-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
902-
MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
940+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2)) {
941+
mcr = mtk_r32(mac->hw, MTK_XMAC_STS_FRC(mac->id));
942+
mcr |= XMAC_FORCE_LINK;
943+
mcr &= ~(XMAC_FORCE_TX_FC | XMAC_FORCE_RX_FC);
944+
/* Configure pause modes -
945+
* phylink will avoid these for half duplex
946+
*/
947+
if (tx_pause)
948+
mcr |= XMAC_FORCE_TX_FC;
949+
if (rx_pause)
950+
mcr |= XMAC_FORCE_RX_FC;
951+
mtk_w32(mac->hw, mcr, MTK_XMAC_STS_FRC(mac->id));
952+
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, 0, MTK_XMAC_MCR(mac->id));
953+
} else {
954+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
955+
MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
903956

904-
mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
905-
mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC |
906-
XMAC_MCR_TRX_DISABLE);
907-
/* Configure pause modes -
908-
* phylink will avoid these for half duplex
909-
*/
910-
if (tx_pause)
911-
mcr |= XMAC_MCR_FORCE_TX_FC;
912-
if (rx_pause)
913-
mcr |= XMAC_MCR_FORCE_RX_FC;
957+
mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
958+
mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
959+
/* Configure pause modes -
960+
* phylink will avoid these for half duplex
961+
*/
962+
if (tx_pause)
963+
mcr |= XMAC_MCR_FORCE_TX_FC;
964+
if (rx_pause)
965+
mcr |= XMAC_MCR_FORCE_RX_FC;
914966

915-
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
967+
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
968+
}
916969
}
917970

918971
static void mtk_mac_link_up(struct phylink_config *config,
@@ -2740,10 +2793,16 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
27402793
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
27412794

27422795
val = MTK_QTX_SCH_MIN_RATE_EN |
2743-
/* minimum: 10 Mbps */
2744-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2745-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
27462796
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2797+
/* minimum: 10 Mbps */
2798+
if (mtk_is_netsys_v3_or_greater(eth) &&
2799+
(eth->soc->caps != MT7988_CAPS)) {
2800+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
2801+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
2802+
} else {
2803+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2804+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
2805+
}
27472806
if (mtk_is_netsys_v1(eth))
27482807
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
27492808
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
@@ -5889,6 +5948,36 @@ static const struct mtk_soc_data mt7986_data = {
58895948
},
58905949
};
58915950

5951+
static const struct mtk_soc_data mt7987_data = {
5952+
.reg_map = &mt7988_reg_map,
5953+
.ana_rgc3 = 0x128,
5954+
.caps = MT7987_CAPS,
5955+
.hw_features = MTK_HW_FEATURES,
5956+
.required_clks = MT7987_CLKS_BITMAP,
5957+
.required_pctl = false,
5958+
.version = 3,
5959+
.offload_version = 2,
5960+
.ppe_num = 2,
5961+
.hash_offset = 4,
5962+
.has_accounting = true,
5963+
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
5964+
//.rss_num = 4,
5965+
.tx = {
5966+
.desc_size = sizeof(struct mtk_tx_dma_v2),
5967+
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5968+
.dma_len_offset = 8,
5969+
.dma_size = MTK_DMA_SIZE(2K),
5970+
.fq_dma_size = MTK_DMA_SIZE(4K),
5971+
},
5972+
.rx = {
5973+
.desc_size = sizeof(struct mtk_rx_dma_v2),
5974+
.dma_l4_valid = RX_DMA_L4_VALID_V2,
5975+
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5976+
.dma_len_offset = 8,
5977+
.dma_size = MTK_DMA_SIZE(2K),
5978+
},
5979+
};
5980+
58925981
static const struct mtk_soc_data mt7988_data = {
58935982
.reg_map = &mt7988_reg_map,
58945983
.ana_rgc3 = 0x128,
@@ -5950,6 +6039,7 @@ const struct of_device_id of_mtk_match[] = {
59506039
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
59516040
{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
59526041
{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
6042+
{ .compatible = "mediatek,mt7987-eth", .data = &mt7987_data },
59536043
{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
59546044
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
59556045
{},

‎drivers/net/ethernet/mediatek/mtk_eth_soc.h‎

Lines changed: 57 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,13 @@
262262
#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
263263
#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
264264

265+
#define MTK_QTX_SCH_MAX_RATE_EN_V3 BIT(26)
266+
#define MTK_QTX_SCH_MIN_RATE_MAN_V3 GENMASK(25, 19)
267+
#define MTK_QTX_SCH_MIN_RATE_EXP_V3 GENMASK(18, 16)
268+
#define MTK_QTX_SCH_MAX_RATE_WEIGHT_V3 GENMASK(15, 10)
269+
#define MTK_QTX_SCH_MAX_RATE_MAN_V3 GENMASK(9, 3)
270+
#define MTK_QTX_SCH_MAX_RATE_EXP_V3 GENMASK(2, 0)
271+
265272
/* QDMA TX Scheduler Rate Control Register */
266273
#define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
267274

@@ -538,9 +545,23 @@
538545
#define XMAC_MCR_FORCE_RX_FC BIT(4)
539546

540547
/* XFI Mac logic reset registers */
541-
#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
548+
#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + \
549+
(MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2) ? \
550+
0x820 : 0x10))
542551
#define XMAC_LOGIC_RST BIT(0)
543552

553+
/* XFI Mac status force registers */
554+
#define MTK_XMAC_STS(x) (MTK_XMAC_MCR(x) + 0x14)
555+
556+
/* XFI Mac status force registers */
557+
#define MTK_XMAC_STS_FRC(x) (MTK_XMAC_MCR(x) + 0x18)
558+
#define XMAC_FORCE_RX_FC_MODE BIT(13)
559+
#define XMAC_FORCE_TX_FC_MODE BIT(12)
560+
#define XMAC_FORCE_LINK_MODE BIT(8)
561+
#define XMAC_FORCE_RX_FC BIT(5)
562+
#define XMAC_FORCE_TX_FC BIT(4)
563+
#define XMAC_FORCE_LINK BIT(0)
564+
544565
/* XFI Mac count global control */
545566
#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
546567
#define XMAC_GLB_CNTCLR BIT(0)
@@ -855,6 +876,17 @@ enum mtk_clks_map {
855876
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
856877
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
857878
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
879+
#define MT7987_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP1) | \
880+
BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP3) | \
881+
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
882+
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
883+
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
884+
BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
885+
BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
886+
BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
887+
BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
888+
BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
889+
BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL))
858890
#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
859891
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
860892
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
@@ -1012,12 +1044,14 @@ enum mkt_eth_capabilities {
10121044
MTK_RSTCTRL_PPE2_BIT,
10131045
MTK_U3_COPHY_V2_BIT,
10141046
MTK_SRAM_BIT,
1047+
MTK_XGMAC_BIT,
1048+
MTK_XGMAC_V2_BIT,
10151049
MTK_36BIT_DMA_BIT,
10161050

10171051
/* MUX BITS*/
10181052
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
10191053
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
1020-
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
1054+
MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT,
10211055
MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
10221056
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
10231057
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
@@ -1059,14 +1093,16 @@ enum mkt_eth_capabilities {
10591093
#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
10601094
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
10611095
#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
1096+
#define MTK_XGMAC BIT_ULL(MTK_XGMAC_BIT)
1097+
#define MTK_XGMAC_V2 BIT_ULL(MTK_XGMAC_V2_BIT)
10621098
#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
10631099

10641100
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
10651101
BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
10661102
#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
10671103
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1068-
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
1069-
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1104+
#define MTK_ETH_MUX_U3_GMAC23_TO_QPHY \
1105+
BIT_ULL(MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT)
10701106
#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
10711107
BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
10721108
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1098,12 +1134,13 @@ enum mkt_eth_capabilities {
10981134
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
10991135
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
11001136
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1101-
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
1137+
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC)
1138+
#define MTK_GMAC2_2P5GPHY_V2 (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC_V2)
11021139
#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
11031140
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1104-
#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
1105-
#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
1106-
#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
1141+
#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII | MTK_XGMAC)
1142+
#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII | MTK_XGMAC)
1143+
#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII | MTK_XGMAC)
11071144

11081145
/* MUXes present on SoCs */
11091146
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1113,9 +1150,9 @@ enum mkt_eth_capabilities {
11131150
#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
11141151
(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
11151152

1116-
/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1117-
#define MTK_MUX_U3_GMAC2_TO_QPHY \
1118-
(MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1153+
/* 0: U3 -> QPHY, 1: GMACx -> QPHY where x is 2 or 3 */
1154+
#define MTK_MUX_U3_GMAC23_TO_QPHY \
1155+
(MTK_ETH_MUX_U3_GMAC23_TO_QPHY | MTK_MUX | MTK_INFRA)
11191156

11201157
/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
11211158
#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1155,18 +1192,25 @@ enum mkt_eth_capabilities {
11551192
#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
11561193
MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
11571194
MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1158-
MTK_MUX_U3_GMAC2_TO_QPHY | \
1195+
MTK_MUX_U3_GMAC23_TO_QPHY | \
11591196
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
11601197

11611198
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
11621199
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1163-
MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1200+
MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
11641201
MTK_RSTCTRL_PPE1 | MTK_SRAM)
11651202

11661203
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
11671204
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
11681205
MTK_RSTCTRL_PPE1 | MTK_SRAM)
11691206

1207+
#define MT7987_CAPS (MTK_36BIT_DMA | MTK_GMAC1_SGMII | \
1208+
MTK_GMAC2_2P5GPHY_V2 | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
1209+
MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
1210+
MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
1211+
MTK_QDMA | /*MTK_PDMA_INT | MTK_RSS |*/ \
1212+
MTK_RSTCTRL_PPE1)
1213+
11701214
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
11711215
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
11721216
MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \

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