clk: mt7987-infra: convert invalid GATE to MUX

Author: frank-w

drivers/clk/mediatek/clk-mt7987-infracfg.c

@@ -51,37 +51,37 @@ static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
 };
 static struct mtk_mux infra_muxes[] = {
 	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
 			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+			     0, 1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
 			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+			     1, 1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
 			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+			     2, 1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
 			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+			     1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
 			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_BCK_SEL,
+			     1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_BCK_SEL,
 			     "infra_mux_spi2_bck_sel",
 			     infra_mux_spi2_bck_parents, 0x0018, 0x0010,
-			     0x0014, 6, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel",
+			     0x0014, 6, 1, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel",
 			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
+			     2, -1, -1),
 	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+	MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
 			     "infra_pcie_gfmux_tl_ck_o_p0_sel",
 			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+			     0x0020, 0x0024, 0, 2, -1, -1),
+	MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
 			     "infra_pcie_gfmux_tl_ck_o_p1_sel",
 			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
+			     0x0020, 0x0024, 2, 2, -1, -1),
 };
 static const struct mtk_gate_regs infra0_cg_regs = {
 	.set_ofs = 0x10,