Skip to content

Commit b151530

Browse files
charliu-AMDENGgregkh
charliu-AMDENG
authored and
gregkh
committed
drm/amd/display: disable DPP RCG before DPP CLK enable
[ Upstream commit 1bcd679 ] [why] DPP CLK enable needs to disable DPPCLK RCG first. The DPPCLK_en in dccg should always be enabled when the corresponding pipe is enabled. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Stable-dep-of: cfa0904 ("drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched") Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent 467904a commit b151530

2 files changed

Lines changed: 38 additions & 21 deletions

File tree

‎drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c‎

Lines changed: 24 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -391,6 +391,7 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg,
391391

392392
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
393393

394+
394395
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)
395396
return;
396397

@@ -411,6 +412,8 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg,
411412
BREAK_TO_DEBUGGER();
412413
break;
413414
}
415+
//DC_LOG_DEBUG("%s: inst(%d) DPPCLK rcg_disable: %d\n", __func__, inst, enable ? 0 : 1);
416+
414417
}
415418

416419
static void dccg35_set_dpstreamclk_rcg(
@@ -1112,30 +1115,24 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg,
11121115
{
11131116
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
11141117

1118+
11151119
switch (dpp_inst) {
11161120
case 0:
11171121
REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);
1118-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
1119-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable);
11201122
break;
11211123
case 1:
11221124
REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);
1123-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
1124-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable);
11251125
break;
11261126
case 2:
11271127
REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);
1128-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
1129-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable);
11301128
break;
11311129
case 3:
11321130
REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);
1133-
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
1134-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable);
11351131
break;
11361132
default:
11371133
break;
11381134
}
1135+
//DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);
11391136

11401137
}
11411138

@@ -1163,14 +1160,18 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,
11631160
ASSERT(false);
11641161
phase = 0xff;
11651162
}
1163+
dccg35_set_dppclk_rcg(dccg, dpp_inst, false);
11661164

11671165
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
11681166
DPPCLK0_DTO_PHASE, phase,
11691167
DPPCLK0_DTO_MODULO, modulo);
11701168

11711169
dcn35_set_dppclk_enable(dccg, dpp_inst, true);
1172-
} else
1170+
} else {
11731171
dcn35_set_dppclk_enable(dccg, dpp_inst, false);
1172+
/*we have this in hwss: disable_plane*/
1173+
//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);
1174+
}
11741175
dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
11751176
}
11761177

@@ -1182,6 +1183,7 @@ static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,
11821183
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
11831184
return;
11841185

1186+
11851187
switch (dpp_inst) {
11861188
case 0:
11871189
REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable);
@@ -1198,6 +1200,8 @@ static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,
11981200
default:
11991201
break;
12001202
}
1203+
//DC_LOG_DEBUG("%s: dpp_inst(%d) rcg: %d\n", __func__, dpp_inst, enable);
1204+
12011205
}
12021206

12031207
static void dccg35_get_pixel_rate_div(
@@ -1521,28 +1525,30 @@ static void dccg35_set_physymclk_root_clock_gating(
15211525
switch (phy_inst) {
15221526
case 0:
15231527
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
1524-
PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
1528+
PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);
15251529
break;
15261530
case 1:
15271531
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
1528-
PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
1532+
PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);
15291533
break;
15301534
case 2:
15311535
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
1532-
PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
1536+
PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);
15331537
break;
15341538
case 3:
15351539
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
1536-
PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
1540+
PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);
15371541
break;
15381542
case 4:
15391543
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
1540-
PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);
1544+
PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);
15411545
break;
15421546
default:
15431547
BREAK_TO_DEBUGGER();
15441548
return;
15451549
}
1550+
//DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE:\n", __func__, phy_inst, enable ? 0 : 1);
1551+
15461552
}
15471553

15481554
static void dccg35_set_physymclk(
@@ -1643,6 +1649,8 @@ static void dccg35_dpp_root_clock_control(
16431649
return;
16441650

16451651
if (clock_on) {
1652+
dccg35_set_dppclk_rcg(dccg, dpp_inst, false);
1653+
16461654
/* turn off the DTO and leave phase/modulo at max */
16471655
dcn35_set_dppclk_enable(dccg, dpp_inst, 1);
16481656
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
@@ -1654,6 +1662,8 @@ static void dccg35_dpp_root_clock_control(
16541662
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
16551663
DPPCLK0_DTO_PHASE, 0,
16561664
DPPCLK0_DTO_MODULO, 1);
1665+
/*we have this in hwss: disable_plane*/
1666+
//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);
16571667
}
16581668

16591669
dccg->dpp_clock_gated[dpp_inst] = !clock_on;

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -241,11 +241,6 @@ void dcn35_init_hw(struct dc *dc)
241241
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
242242
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
243243
}
244-
if (res_pool->dccg->funcs->dccg_root_gate_disable_control) {
245-
for (i = 0; i < res_pool->pipe_count; i++)
246-
res_pool->dccg->funcs->dccg_root_gate_disable_control(res_pool->dccg, i, 0);
247-
}
248-
249244
for (i = 0; i < res_pool->audio_count; i++) {
250245
struct audio *audio = res_pool->audios[i];
251246

@@ -885,12 +880,18 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
885880
void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
886881
struct dc_state *context)
887882
{
883+
struct dpp *dpp = pipe_ctx->plane_res.dpp;
884+
struct dccg *dccg = dc->res_pool->dccg;
885+
886+
888887
/* enable DCFCLK current DCHUB */
889888
pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
890889

891890
/* initialize HUBP on power up */
892891
pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
893-
892+
/*make sure DPPCLK is on*/
893+
dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);
894+
dpp->funcs->dpp_dppclk_control(dpp, false, true);
894895
/* make sure OPP_PIPE_CLOCK_EN = 1 */
895896
pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
896897
pipe_ctx->stream_res.opp,
@@ -907,6 +908,7 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
907908
// Program system aperture settings
908909
pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
909910
}
911+
//DC_LOG_DEBUG("%s: dpp_inst(%d) =\n", __func__, dpp->inst);
910912

911913
if (!pipe_ctx->top_pipe
912914
&& pipe_ctx->plane_state
@@ -922,6 +924,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
922924
{
923925
struct hubp *hubp = pipe_ctx->plane_res.hubp;
924926
struct dpp *dpp = pipe_ctx->plane_res.dpp;
927+
struct dccg *dccg = dc->res_pool->dccg;
928+
925929

926930
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
927931

@@ -939,7 +943,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
939943
hubp->funcs->hubp_clk_cntl(hubp, false);
940944

941945
dpp->funcs->dpp_dppclk_control(dpp, false, false);
942-
/*to do, need to support both case*/
946+
dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);
947+
943948
hubp->power_gated = true;
944949

945950
hubp->funcs->hubp_reset(hubp);
@@ -951,6 +956,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
951956
pipe_ctx->top_pipe = NULL;
952957
pipe_ctx->bottom_pipe = NULL;
953958
pipe_ctx->plane_state = NULL;
959+
//DC_LOG_DEBUG("%s: dpp_inst(%d)=\n", __func__, dpp->inst);
960+
954961
}
955962

956963
void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

0 commit comments

Comments
 (0)