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Merge tag 'v6.1.144' into 6.1-main
This is the 6.1.144 stable release # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAmhvx2UACgkQONu9yGCS # aT5hlBAAvC7s51HMJIleGSVUyEkRspvEMKiRfiZv0FWVr+4YPruQoQZUaAczUqhE # rvp56l/GZpAGiX/7vPdt0EDbuzgD9K/XKASWK+lT9ZV1vLwhn1T2pM6HHSPcBH0Q # Mg59pkIB4qM/3HHfVW/syovU8I2nnghAXDPBsw4kYdG1gtT4+kEDv6lTWGf76rEa # ZkRUIX87EvPbWSxP+bYiIXDQ6FfV+p3giK5rJV6gAK/oYPNHZUPVoBzLR37V8NkB # ns1cATpnzdq3uZ6LvHkDhMZa8E9mQ6XZhQxw1I4rUEweEooM6vBWyVtHlLzdBtwm # RDMD+4knCNvP00Qn4k9SviTISI2TWjVZ+QBreHoM4xOnlNhpzlUXFs59BPvD/lFD # D1bV7mtBuYXTq5jNEt7Tqn4g4CCOKRQZw8/1FmfBuTsrKrENcDiftWtiYBQkHNpa # MSgHDd+YEiRgma0HJVv8689xSRMbOg3mZKafiD2XUI1rhCKHe/oU9QzjOTUHIIDP # YgP6dUvSekmdlAd/bIGAurCFVnf43KnjVo2oHxTBSAGVt5vcUyiFt94PRoF7EVWM # 7khGwBjWNlaQEMjoINx/k4W08qoGUm1xQouMskOILRN1mGWg/D49qVfEc86b4jhX # 8rC+wGdXGQBoX6+ehEjaMWGL55zItSsy543QFlTHIWfwjo+X7eo= # =tQjF # -----END PGP SIGNATURE----- # gpg: Signature made Thu Jul 10 16:00:05 2025 CEST # gpg: using RSA key 647F28654894E3BD457199BE38DBBDC86092693E # gpg: Can't check signature: No public key
2 parents 25aa440 + dfc486e commit cbfab53

105 files changed

Lines changed: 970 additions & 303 deletions

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‎Documentation/ABI/testing/sysfs-devices-system-cpu‎

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@@ -526,6 +526,7 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/spectre_v1
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/sys/devices/system/cpu/vulnerabilities/spectre_v2
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/sys/devices/system/cpu/vulnerabilities/srbds
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/sys/devices/system/cpu/vulnerabilities/tsa
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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Date: January 2018
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Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>

‎Documentation/ABI/testing/sysfs-driver-ufs‎

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@@ -711,7 +711,7 @@ Description: This file shows the thin provisioning type. This is one of
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The file is read only.
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What: /sys/class/scsi_device/*/device/unit_descriptor/physical_memory_resourse_count
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What: /sys/class/scsi_device/*/device/unit_descriptor/physical_memory_resource_count
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Date: February 2018
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Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
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Description: This file shows the total physical memory resources. This is

‎Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst‎

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@@ -157,9 +157,7 @@ This is achieved by using the otherwise unused and obsolete VERW instruction in
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combination with a microcode update. The microcode clears the affected CPU
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buffers when the VERW instruction is executed.
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Kernel reuses the MDS function to invoke the buffer clearing:
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mds_clear_cpu_buffers()
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Kernel does the buffer clearing with x86_clear_cpu_buffers().
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On MDS affected CPUs, the kernel already invokes CPU buffer clear on
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kernel/userspace, hypervisor/guest and C-state (idle) transitions. No

‎Documentation/admin-guide/kernel-parameters.txt‎

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If not specified, "default" is used. In this case,
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the RNG's choice is left to each individual trust source.
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tsa= [X86] Control mitigation for Transient Scheduler
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Attacks on AMD CPUs. Search the following in your
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favourite search engine for more details:
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"Technical guidance for mitigating transient scheduler
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attacks".
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off - disable the mitigation
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on - enable the mitigation (default)
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user - mitigate only user/kernel transitions
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vm - mitigate only guest/host transitions
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tsc= Disable clocksource stability checks for TSC.
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Format: <string>
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[x86] reliable: mark tsc clocksource as reliable, this

‎Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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VERSION = 6
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PATCHLEVEL = 1
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SUBLEVEL = 143
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SUBLEVEL = 144
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EXTRAVERSION =
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NAME = Curry Ramen
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‎arch/arm64/boot/dts/apple/t8103-jxxx.dtsi‎

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*/
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&port00 {
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bus-range = <1 1>;
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wifi0: network@0,0 {
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wifi0: wifi@0,0 {
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compatible = "pci14e4,4425";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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/* To be filled by the loader */

‎arch/powerpc/include/uapi/asm/ioctls.h‎

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@@ -23,10 +23,10 @@
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#define TCSETSW _IOW('t', 21, struct termios)
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#define TCSETSF _IOW('t', 22, struct termios)
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#define TCGETA _IOR('t', 23, struct termio)
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#define TCSETA _IOW('t', 24, struct termio)
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#define TCSETAW _IOW('t', 25, struct termio)
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#define TCSETAF _IOW('t', 28, struct termio)
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#define TCGETA 0x40147417 /* _IOR('t', 23, struct termio) */
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#define TCSETA 0x80147418 /* _IOW('t', 24, struct termio) */
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#define TCSETAW 0x80147419 /* _IOW('t', 25, struct termio) */
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#define TCSETAF 0x8014741c /* _IOW('t', 28, struct termio) */
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#define TCSBRK _IO('t', 29)
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#define TCXONC _IO('t', 30)

‎arch/s390/pci/pci_event.c‎

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struct zpci_dev *zdev = to_zpci(pdev);
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int rc;
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/* The underlying device may have been disabled by the event */
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if (!zdev_enabled(zdev))
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return PCI_ERS_RESULT_NEED_RESET;
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pr_info("%s: Unblocking device access for examination\n", pci_name(pdev));
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rc = zpci_reset_load_store_blocked(zdev);
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if (rc) {

‎arch/x86/Kconfig‎

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disabled, mitigation cannot be enabled via cmdline.
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See <file:Documentation/admin-guide/hw-vuln/indirect-target-selection.rst>
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config MITIGATION_TSA
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bool "Mitigate Transient Scheduler Attacks"
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depends on CPU_SUP_AMD
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default y
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help
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Enable mitigation for Transient Scheduler Attacks. TSA is a hardware
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security vulnerability on AMD CPUs which can lead to forwarding of
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invalid info to subsequent instructions and thus can affect their
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timing and thereby cause a leakage.
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endif
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config ARCH_HAS_ADD_PAGES

‎arch/x86/entry/entry.S‎

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@@ -31,20 +31,20 @@ EXPORT_SYMBOL_GPL(entry_ibpb);
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/*
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* Define the VERW operand that is disguised as entry code so that
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* it can be referenced with KPTI enabled. This ensure VERW can be
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* it can be referenced with KPTI enabled. This ensures VERW can be
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* used late in exit-to-user path after page tables are switched.
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*/
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.pushsection .entry.text, "ax"
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.align L1_CACHE_BYTES, 0xcc
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SYM_CODE_START_NOALIGN(mds_verw_sel)
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SYM_CODE_START_NOALIGN(x86_verw_sel)
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR
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.word __KERNEL_DS
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.align L1_CACHE_BYTES, 0xcc
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SYM_CODE_END(mds_verw_sel);
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SYM_CODE_END(x86_verw_sel);
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/* For KVM */
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EXPORT_SYMBOL_GPL(mds_verw_sel);
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EXPORT_SYMBOL_GPL(x86_verw_sel);
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.popsection
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