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bcchen28411frank-w
bcchen28411
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frank-w
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net: ethernet: mtk_eth_soc: add mt7987 support
Without this patch, users are unable to bring up ETH driver on the mt7987. Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com> --- squashed: net: mtk_eth_soc: drop MTK_SRAM as it is too small for DMA RX/TX rings
1 parent cc0fd15 commit e69d41f

3 files changed

Lines changed: 177 additions & 42 deletions

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‎drivers/net/ethernet/mediatek/mtk_eth_path.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -106,13 +106,14 @@ static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)
106106
return 0;
107107
}
108108

109-
static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
109+
static int set_mux_u3_gmac23_to_qphy(struct mtk_eth *eth, u64 path)
110110
{
111111
unsigned int val = 0, mask = 0, reg = 0;
112112
bool updated = true;
113113

114114
switch (path) {
115115
case MTK_ETH_PATH_GMAC2_SGMII:
116+
case MTK_ETH_PATH_GMAC3_SGMII:
116117
if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
117118
reg = USB_PHY_SWITCH_REG;
118119
val = SGMII_QPHY_SEL;
@@ -283,9 +284,9 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
283284
.cap_bit = MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY,
284285
.set_path = set_mux_gmac2_gmac0_to_gephy,
285286
}, {
286-
.name = "mux_u3_gmac2_to_qphy",
287-
.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
288-
.set_path = set_mux_u3_gmac2_to_qphy,
287+
.name = "mux_u3_gmac23_to_qphy",
288+
.cap_bit = MTK_ETH_MUX_U3_GMAC23_TO_QPHY,
289+
.set_path = set_mux_u3_gmac23_to_qphy,
289290
}, {
290291
.name = "mux_gmac2_to_2p5gphy",
291292
.cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,

‎drivers/net/ethernet/mediatek/mtk_eth_soc.c‎

Lines changed: 116 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -576,9 +576,14 @@ static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
576576
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE,
577577
XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
578578

579-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) |
580-
MTK_XGMAC_FORCE_LINK(mac->id),
581-
MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id));
579+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2))
580+
mtk_m32(mac->hw, XMAC_FORCE_RX_FC_MODE | XMAC_FORCE_TX_FC_MODE |
581+
XMAC_FORCE_LINK_MODE | XMAC_FORCE_LINK,
582+
XMAC_FORCE_RX_FC_MODE | XMAC_FORCE_TX_FC_MODE |
583+
XMAC_FORCE_LINK_MODE, MTK_XMAC_STS_FRC(mac->id));
584+
else
585+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) | MTK_XGMAC_FORCE_LINK(mac->id),
586+
MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id));
582587
}
583588

584589
return 0;
@@ -778,6 +783,7 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
778783
{
779784
struct mtk_mac *mac = container_of(config, struct mtk_mac,
780785
phylink_config);
786+
struct mtk_eth *eth = mac->hw;
781787

782788
if (!mtk_interface_mode_is_xgmii(mac->hw, interface)) {
783789
/* GMAC modes */
@@ -787,12 +793,14 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
787793
if (mtk_is_netsys_v3_or_greater(mac->hw))
788794
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
789795
MTK_XGMAC_STS(mac->id));
790-
} else if (mac->id != MTK_GMAC1_ID) {
796+
} else if (mtk_is_netsys_v3_or_greater(mac->hw) && mac->id != MTK_GMAC1_ID) {
791797
/* XGMAC except for built-in switch */
792798
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE,
793799
MTK_XMAC_MCR(mac->id));
794-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
795-
MTK_XGMAC_STS(mac->id));
800+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2))
801+
mtk_m32(mac->hw, XMAC_FORCE_LINK, 0, MTK_XMAC_STS_FRC(mac->id));
802+
else
803+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
796804
}
797805
}
798806

@@ -806,10 +814,16 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
806814
return;
807815

808816
val = MTK_QTX_SCH_MIN_RATE_EN |
809-
/* minimum: 10 Mbps */
810-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
811-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
812817
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
818+
/* minimum: 10 Mbps */
819+
if (mtk_is_netsys_v3_or_greater(eth) &&
820+
(eth->soc->caps != MT7988_CAPS)) {
821+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
822+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
823+
} else {
824+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
825+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
826+
}
813827
if (mtk_is_netsys_v1(eth))
814828
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
815829

@@ -836,6 +850,30 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
836850
default:
837851
break;
838852
}
853+
} else if (mtk_is_netsys_v3_or_greater(eth) &&
854+
(eth->soc->caps != MT7988_CAPS)) {
855+
switch (speed) {
856+
case SPEED_10:
857+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
858+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
859+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 4) |
860+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
861+
break;
862+
case SPEED_100:
863+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
864+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
865+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 5) |
866+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 1);
867+
break;
868+
case SPEED_1000:
869+
val |= MTK_QTX_SCH_MAX_RATE_EN_V3 |
870+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN_V3, 1) |
871+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP_V3, 6) |
872+
FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT_V3, 10);
873+
break;
874+
default:
875+
break;
876+
}
839877
} else {
840878
switch (speed) {
841879
case SPEED_10:
@@ -910,6 +948,7 @@ static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
910948
int speed, int duplex, bool tx_pause,
911949
bool rx_pause)
912950
{
951+
struct mtk_eth *eth = mac->hw;
913952
u32 mcr;
914953

915954
if (mac->id == MTK_GMAC1_ID)
@@ -921,21 +960,35 @@ static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
921960
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
922961
MTK_XMAC_CNT_CTRL(mac->id));
923962

924-
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
925-
MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
963+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2)) {
964+
mcr = mtk_r32(mac->hw, MTK_XMAC_STS_FRC(mac->id));
965+
mcr |= XMAC_FORCE_LINK;
966+
mcr &= ~(XMAC_FORCE_TX_FC | XMAC_FORCE_RX_FC);
967+
/* Configure pause modes -
968+
* phylink will avoid these for half duplex
969+
*/
970+
if (tx_pause)
971+
mcr |= XMAC_FORCE_TX_FC;
972+
if (rx_pause)
973+
mcr |= XMAC_FORCE_RX_FC;
974+
mtk_w32(mac->hw, mcr, MTK_XMAC_STS_FRC(mac->id));
975+
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, 0, MTK_XMAC_MCR(mac->id));
976+
} else {
977+
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
978+
MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
926979

927-
mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
928-
mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC |
929-
XMAC_MCR_TRX_DISABLE);
930-
/* Configure pause modes -
931-
* phylink will avoid these for half duplex
932-
*/
933-
if (tx_pause)
934-
mcr |= XMAC_MCR_FORCE_TX_FC;
935-
if (rx_pause)
936-
mcr |= XMAC_MCR_FORCE_RX_FC;
980+
mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
981+
mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
982+
/* Configure pause modes -
983+
* phylink will avoid these for half duplex
984+
*/
985+
if (tx_pause)
986+
mcr |= XMAC_MCR_FORCE_TX_FC;
987+
if (rx_pause)
988+
mcr |= XMAC_MCR_FORCE_RX_FC;
937989

938-
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
990+
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
991+
}
939992
}
940993

941994
static void mtk_mac_link_up(struct phylink_config *config,
@@ -2735,10 +2788,16 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
27352788
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
27362789

27372790
val = MTK_QTX_SCH_MIN_RATE_EN |
2738-
/* minimum: 10 Mbps */
2739-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2740-
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
27412791
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2792+
/* minimum: 10 Mbps */
2793+
if (mtk_is_netsys_v3_or_greater(eth) &&
2794+
(eth->soc->caps != MT7988_CAPS)) {
2795+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN_V3, 1) |
2796+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP_V3, 4);
2797+
} else {
2798+
val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2799+
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4);
2800+
}
27422801
if (mtk_is_netsys_v1(eth))
27432802
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
27442803
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
@@ -6445,6 +6504,37 @@ static const struct mtk_soc_data mt7986_data = {
64456504
},
64466505
};
64476506

6507+
static const struct mtk_soc_data mt7987_data = {
6508+
.reg_map = &mt7988_reg_map,
6509+
.ana_rgc3 = 0x128,
6510+
.caps = MT7987_CAPS,
6511+
.hw_features = MTK_HW_FEATURES,
6512+
.required_clks = MT7987_CLKS_BITMAP,
6513+
.required_pctl = false,
6514+
.version = 3,
6515+
.offload_version = 2,
6516+
.ppe_num = 2,
6517+
.hash_offset = 4,
6518+
.has_accounting = true,
6519+
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
6520+
//.rss_num = 4,
6521+
.tx = {
6522+
.desc_size = sizeof(struct mtk_tx_dma_v2),
6523+
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
6524+
.dma_len_offset = 8,
6525+
.dma_size = MTK_DMA_SIZE(2K),
6526+
.fq_dma_size = MTK_DMA_SIZE(4K),
6527+
},
6528+
.rx = {
6529+
.desc_size = sizeof(struct mtk_rx_dma_v2),
6530+
.irq_done_mask = MTK_RX_DONE_INT_V2,
6531+
.dma_l4_valid = RX_DMA_L4_VALID_V2,
6532+
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
6533+
.dma_len_offset = 8,
6534+
.dma_size = MTK_DMA_SIZE(2K),
6535+
},
6536+
};
6537+
64486538
static const struct mtk_soc_data mt7988_data = {
64496539
.reg_map = &mt7988_reg_map,
64506540
.ana_rgc3 = 0x128,
@@ -6506,6 +6596,7 @@ const struct of_device_id of_mtk_match[] = {
65066596
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
65076597
{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
65086598
{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
6599+
{ .compatible = "mediatek,mt7987-eth", .data = &mt7987_data },
65096600
{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
65106601
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
65116602
{},

‎drivers/net/ethernet/mediatek/mtk_eth_soc.h‎

Lines changed: 56 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,13 @@
283283
#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
284284
#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
285285

286+
#define MTK_QTX_SCH_MAX_RATE_EN_V3 BIT(26)
287+
#define MTK_QTX_SCH_MIN_RATE_MAN_V3 GENMASK(25, 19)
288+
#define MTK_QTX_SCH_MIN_RATE_EXP_V3 GENMASK(18, 16)
289+
#define MTK_QTX_SCH_MAX_RATE_WEIGHT_V3 GENMASK(15, 10)
290+
#define MTK_QTX_SCH_MAX_RATE_MAN_V3 GENMASK(9, 3)
291+
#define MTK_QTX_SCH_MAX_RATE_EXP_V3 GENMASK(2, 0)
292+
286293
/* QDMA TX Scheduler Rate Control Register */
287294
#define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
288295

@@ -569,9 +576,23 @@
569576
#define XMAC_MCR_FORCE_RX_FC BIT(4)
570577

571578
/* XFI Mac logic reset registers */
572-
#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
579+
#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + \
580+
(MTK_HAS_CAPS(eth->soc->caps, MTK_XGMAC_V2) ? \
581+
0x820 : 0x10))
573582
#define XMAC_LOGIC_RST BIT(0)
574583

584+
/* XFI Mac status force registers */
585+
#define MTK_XMAC_STS(x) (MTK_XMAC_MCR(x) + 0x14)
586+
587+
/* XFI Mac status force registers */
588+
#define MTK_XMAC_STS_FRC(x) (MTK_XMAC_MCR(x) + 0x18)
589+
#define XMAC_FORCE_RX_FC_MODE BIT(13)
590+
#define XMAC_FORCE_TX_FC_MODE BIT(12)
591+
#define XMAC_FORCE_LINK_MODE BIT(8)
592+
#define XMAC_FORCE_RX_FC BIT(5)
593+
#define XMAC_FORCE_TX_FC BIT(4)
594+
#define XMAC_FORCE_LINK BIT(0)
595+
575596
/* XFI Mac count global control */
576597
#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
577598
#define XMAC_GLB_CNTCLR BIT(0)
@@ -886,6 +907,17 @@ enum mtk_clks_map {
886907
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
887908
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
888909
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
910+
#define MT7987_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP1) | \
911+
BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP3) | \
912+
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
913+
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
914+
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
915+
BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
916+
BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
917+
BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
918+
BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
919+
BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
920+
BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL))
889921
#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
890922
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
891923
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
@@ -1071,12 +1103,14 @@ enum mkt_eth_capabilities {
10711103
MTK_RSTCTRL_PPE2_BIT,
10721104
MTK_U3_COPHY_V2_BIT,
10731105
MTK_SRAM_BIT,
1106+
MTK_XGMAC_BIT,
1107+
MTK_XGMAC_V2_BIT,
10741108
MTK_36BIT_DMA_BIT,
10751109

10761110
/* MUX BITS*/
10771111
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
10781112
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
1079-
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
1113+
MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT,
10801114
MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
10811115
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
10821116
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
@@ -1120,14 +1154,16 @@ enum mkt_eth_capabilities {
11201154
#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
11211155
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
11221156
#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
1157+
#define MTK_XGMAC BIT_ULL(MTK_XGMAC_BIT)
1158+
#define MTK_XGMAC_V2 BIT_ULL(MTK_XGMAC_V2_BIT)
11231159
#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
11241160

11251161
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
11261162
BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
11271163
#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
11281164
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1129-
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
1130-
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1165+
#define MTK_ETH_MUX_U3_GMAC23_TO_QPHY \
1166+
BIT_ULL(MTK_ETH_MUX_U3_GMAC23_TO_QPHY_BIT)
11311167
#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
11321168
BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
11331169
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1159,12 +1195,13 @@ enum mkt_eth_capabilities {
11591195
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
11601196
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
11611197
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1162-
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
1198+
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC)
1199+
#define MTK_GMAC2_2P5GPHY_V2 (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY | MTK_XGMAC_V2)
11631200
#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
11641201
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1165-
#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
1166-
#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
1167-
#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
1202+
#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII | MTK_XGMAC)
1203+
#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII | MTK_XGMAC)
1204+
#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII | MTK_XGMAC)
11681205

11691206
/* MUXes present on SoCs */
11701207
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1174,9 +1211,9 @@ enum mkt_eth_capabilities {
11741211
#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
11751212
(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
11761213

1177-
/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1178-
#define MTK_MUX_U3_GMAC2_TO_QPHY \
1179-
(MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1214+
/* 0: U3 -> QPHY, 1: GMACx -> QPHY where x is 2 or 3 */
1215+
#define MTK_MUX_U3_GMAC23_TO_QPHY \
1216+
(MTK_ETH_MUX_U3_GMAC23_TO_QPHY | MTK_MUX | MTK_INFRA)
11801217

11811218
/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
11821219
#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
@@ -1216,18 +1253,24 @@ enum mkt_eth_capabilities {
12161253
#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
12171254
MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
12181255
MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1219-
MTK_MUX_U3_GMAC2_TO_QPHY | \
1256+
MTK_MUX_U3_GMAC23_TO_QPHY | \
12201257
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
12211258

12221259
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
12231260
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1224-
MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1261+
MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
12251262
MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
12261263

12271264
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
12281265
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
12291266
MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
12301267

1268+
#define MT7987_CAPS (MTK_36BIT_DMA | MTK_GMAC1_SGMII | \
1269+
MTK_GMAC2_2P5GPHY_V2 | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
1270+
MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
1271+
MTK_MUX_U3_GMAC23_TO_QPHY | MTK_U3_COPHY_V2 | \
1272+
MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_PDMA_INT | MTK_RSS)
1273+
12311274
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
12321275
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
12331276
MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \

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