feat(dlc10): pure-Rust driver for Xilinx Platform Cable USB II + SPI flash

[gHashTag]

Replace Python tools/dlc10_jtag.py with a pure-Rust driver using rusb (per Article II of the dePIN constitution: Rust only, no .sh, no Vivado, no proprietary toolchain).

What this delivers

• New crate cli/dlc10: library + binary implementing DLC10 control-transfer + JTAG state machine
• Embeds Cypress FX2 firmware (xusb_xp2.hex) and bscan_spi proxy bitstream (MIT, quartiq) via include_bytes!
• Subcommands: idcode, sram <bitfile>, program <bitfile> (SPI flash)
• Rewrite cli/flash-spi to call dlc10::Dlc10::program_flash directly (drops openFPGALoader dependency — DLC10 was never supported there)

Status

• cli/dlc10 crate implemented (12 unit tests passing)
• cargo run -p dlc10 -- idcode returns 0x13631093 (XC7A100T) on hardware
• cargo run -p dlc10 -- sram heartbeat.bit — DONE bit stays LOW (under debug)
• cargo run -p dlc10 -- program target.bit (SPI flash + power-cycle verify)

Refs

• Related: hw: DSLogic JTAG diagnostics — BLOCKER-1 physical debug #590 (DSLogic JTAG diagnostics — physical debug track)
• Related: 🔨 hw: синтез + прошивка + bench на железе (v0.2-igla-fpga Release) trinity-fpga#14 (синтез + прошивка + bench)
• Related: 🛠️ SETUP: Trinity Node-0 — полная настройка первого dePIN-узла (FPGA + headscale + exit node) trinity-fpga#17 (Trinity Node-0 setup)