🎯 ONE SHOT — L-DPC6: USB-3 Trinity Ternary Internet Node

[gHashTag]

🎯 ONE SHOT — TRINITY TERNARY INTERNET NODE

Mission Codename: TRI-NET-G1
Owner Repo: gHashTag/trinity-fpga
Implementation Repo: gHashTag/tt-trinity-gf16
Parent EPIC: #19
AGI Layer: gHashTag/t27#583
Base PR: gHashTag/tt-trinity-gf16#2
Base Branch: feat/trinity-mesh-v0
Current HEAD: 702559b
Priority: P0
Mission Type: FPGA / RTL / DePIN / USB-3 / Mesh
Anchor: phi^2 + phi^-2 = 3

---

0. Hard Rules

1. No Linux in compute core. The FPGA node is a bare RTL computer: packet fabric, GF16/ternary compute tiles, receipt engine, host/mesh ingress. No Linux, no soft CPU, no AXI/IP Integrator in the core path.
2. No new hardware multipliers. Do not introduce arithmetic * in synthesizable RTL. Existing legacy gf16_mul.v is tolerated only as pre-existing substrate; new ternary/GF16 mesh logic must be XOR/popcount/add/FSM/ready-valid only.
3. USB-3 is a boundary, not a processor. Use FT60x-style FIFO boundary for host streaming/programming/readout. Do not pull in vendor black-box IP.
4. Mesh is off-chip at G1/G2. Radio/Wi-Fi/LoRa/Ethernet modules feed packets into FPGA ingress. FPGA does not implement LoRa/Wi-Fi PHY in this mission.
5. TRI settlement is off-chip at G1/G2. FPGA emits deterministic compute receipts; token accounting/verifier/network settlement are separate layers.
6. R5 honesty. Do not claim “Helium competitor complete” until at least two physical nodes exchange jobs and receipts over an external mesh/backhaul.

---

1. Background

tt-trinity-gf16 was originally a combinational GF16 dot4 demonstrator. PR #2 upgrades it into a CPU-less RTL packet fabric v0: host FSM, 2x2 tile fabric, four gf16_dot4 tiles, packetized LOAD_A, LOAD_B, COMPUTE, READ_RES, and RESULT output. The new DePIN extension adds docs/TRINITY_DEPIN_NODE.md, trinity_usb3_fifo_bridge.v, trinity_mesh_adapter_stub.v, and receipt constants without touching TT die pinout.

The product target is a Trinity node: an FPGA that can be programmed/streamed through USB-3, joined to a physical mesh/backhaul, execute Trinity GF16/ternary compute jobs, and emit receipts that can later be settled in TRI. This competes with the incentive pattern of Helium, but changes the unit of value from wireless coverage only to useful ternary compute plus mesh transport.

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2. Hypothesis

H1: A Trinity FPGA node can act as a CPU-less packet-compute endpoint if a PC sends one 32-bit job packet stream over USB-3 FIFO, the FPGA routes it through the on-chip mesh to a GF16/ternary tile, and returns a deterministic RESULT/RECEIPT packet without Linux, soft CPU, or AXI.

Falsification witness: H1 is false if any G1 loopback run cannot reproduce the canonical result 0x47C0 through the packet path, or if the path requires Linux/soft CPU/AXI/new arithmetic multipliers inside the compute core.

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3. Mission Scope

In Scope

• Implement and validate a USB-3 FIFO boundary for Trinity 32-bit packets.
• Preserve PR deps: bump @docusaurus/module-type-aliases from 3.9.2 to 3.10.0 in /docs #2 packet fabric and tile protocol.
• Build a PC-to-FPGA loopback path: PC writes packet stream, FPGA computes, PC reads RESULT/RECEIPT.
• Define receipt fields required for TRI accounting.
• Define clean external mesh/backhaul adapter boundary.
• Produce board-top wrapper for first FPGA devkit target.

Out of Scope

• Full LoRa/Wi-Fi/Ethernet PHY inside FPGA.
• Mainnet TRI settlement.
• Full decentralized routing protocol.
• Custom PCB production before G1/G2 pass.
• Replacing gf16_dot4 with full ternary matmul unless G1 is already green.

---

4. Lane Map

Lane	Owner	Mission	Deliverable	Gate
L-G0	RTL	Stabilize PR #2	feat/trinity-mesh-v0 green CI	GDS green
L-G1	USB-3	FT60x FIFO loopback	trinity_usb3_fifo_bridge wired to board-top	PC reads 0x47C0
L-G2	Host protocol	Packet parser/driver	host tool sends LOAD_A/LOAD_B/COMPUTE/READ_RES	100 repeated jobs pass
L-G3	Mesh adapter	External radio/backhaul boundary	two-node packet exchange over adapter	node B returns receipt
L-G4	TRI receipt	Proof-of-compute receipt	receipt verifier checks job/result/nonce/checksum	invalid result rejected
L-G5	Product board	Custom carrier spec	FPGA + USB-C/FT601 + flash + radio connector	schematic review GO

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5. Pre-Registration

Field	Value
Primary test	Deterministic loopback test
Success criterion	PC receives RESULT/RECEIPT containing 0x47C0 from FPGA packet path
Repetition count	100 consecutive loopbacks
Failure threshold	Any wrong result, dropped packet, lockup, or core dependency on Linux/AXI/soft CPU
Timing target	First G1 target may be functional before throughput optimization
Multiple testing	N/A, single engineering gate
Stop rule	Stop G1 when 100/100 loopbacks pass or a falsification witness is hit

---

6. Technical Architecture

PC host
  |
USB-C / USB-3
  |
FT601 / FT600 FIFO bridge
  |
trinity_usb3_fifo_bridge.v
  |
32-bit Trinity packet ingress / egress
  |
trinity_router_2x2.v
  |
trinity_gf16_tile.v x4
  |
RESULT / RECEIPT packet
  |
PC verifier / TRI settlement layer

External mesh is parallel to USB host ingress:

Radio / Wi-Fi / LoRa / Ethernet module
  |
trinity_mesh_adapter_stub.v
  |
same 32-bit Trinity packet ingress / egress
  |
on-chip packet fabric

The FPGA must see both USB and mesh as packet sources. The packet protocol is the stable boundary; the future Trinity CPU can later replace trinity_master_fsm or act as another packet master without changing tile interfaces.

---

7. Packet and Receipt Contract

Base packet format:

[31:28] op
[27:26] dst
[25:24] src
[23:20] lane
[19:16] reserved
[15:0] payload

Receipt extension:

Field	Width	Purpose
compute_job_id	16	Job identity from host/network
tile_id	2	Tile that executed job
op_code	4	GF16/ternary operation
result	16	Computed result
nonce	16	Replay resistance placeholder
checksum	8	Lightweight integrity placeholder

G4 must replace checksum placeholder with a real verifier contract. Until then, receipts are deterministic engineering artifacts, not final TRI payment proofs.

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8. Quality Gates

Gate	Required Evidence	GO Criteria
G0	PR #2 CI	gds green, no failing checks
G1	USB-3 loopback log	100/100 packet jobs return 0x47C0
G2	Host driver test	PC sends arbitrary packet sequence and reads result
G3	Two-node demo	Node A sends job through external adapter, Node B returns receipt
G4	Receipt verifier	Bad result/nonce/checksum rejected
G5	Hardware review	Carrier schematic has FPGA, USB-C/FT601, flash, JTAG/SPI, radio connector

No gate may be marked green from intention. Each gate requires logs, commit SHA, and a repeatable command or hardware test recipe.

---

9. Implementation Orders

Order A — Close PR #2

1. Wait for GDS check on PR deps: bump @docusaurus/module-type-aliases from 3.9.2 to 3.10.0 in /docs #2.
2. If green, merge or mark ready for owner review.
3. If red, fix only the failing synthesis/GDS cause. Do not expand mission scope.

Order B — G1 USB-3 FIFO Loopback

1. Choose devkit: QMTECH XC7A100T or equivalent Artix-7 board with enough I/O for FT60x FIFO.
2. Use FT601 if available: 32-bit FIFO path matches Trinity packet width.
3. Add boards/qmtech_a100t/top_usb3_loopback.v.
4. Add CDC/async FIFO between FT60x clock domain and 50 MHz Trinity fabric if clocks differ.
5. Host sends canonical job packet stream.
6. FPGA returns RESULT/RECEIPT.
7. Record 100/100 pass/fail log.

Order C — G2 Host Packet Tool

1. Minimal host tool: open USB device, write 32-bit packets, read 32-bit result packets.
2. No blockchain logic in G2.
3. Output JSONL receipt log:

{"job_id":1,"tile_id":0,"op":"GF16_DOT4","expected":"0x47C0","observed":"0x47C0","status":"pass"}

Order D — G3 Mesh Adapter

1. Pick physical transport after G2: Ethernet/Wi-Fi module for bandwidth, LoRa for low-rate coverage, or both.
2. Adapter converts external frames into Trinity packets.
3. Demonstrate two physical nodes exchanging one compute job.

Order E — G4 TRI Receipt Verifier

1. Define off-chain verifier first.
2. Verify job/result/nonce/checksum.
3. Reject replay and wrong result.
4. Only after this define token settlement mechanics.

---

10. Forbidden Actions

• Do not introduce Linux as a required component of the FPGA compute node.
• Do not hide GDS/CI failures.
• Do not claim mesh internet before two physical nodes pass G3.
• Do not order custom PCB before G1 and G2.
• Do not mix token economics into RTL before receipt correctness is stable.
• Do not add vendor encrypted IP to the open RTL path.
• Do not replace the stable packet interface while the future Trinity CPU is not ready.

---

11. Active Artifacts

• PR deps: bump @docusaurus/module-type-aliases from 3.9.2 to 3.10.0 in /docs #2: feat: Trinity v0 RTL mesh fabric (CPU-less, GF16 dot4 tiles) tt-trinity-gf16#2
• Current branch: feat/trinity-mesh-v0
• Current HEAD: 702559b
• RTL mesh v0 files:
  • src/trinity_packet.vh
  • src/trinity_gf16_tile.v
  • src/trinity_router_2x2.v
  • src/trinity_mesh_2x2.v
  • src/trinity_master_fsm.v
• DePIN boundary files:
  • docs/TRINITY_DEPIN_NODE.md
  • src/trinity_usb3_fifo_bridge.v
  • src/trinity_mesh_adapter_stub.v

---

12. GO / NO-GO Poll

Component	Call
PR #2 as architecture base	GO
Merge PR #2 before GDS green	NO-GO
G1 USB-3 loopback	GO
G2 host packet tool	GO after G1 RTL wiring
G3 physical mesh	HOLD until G2
TRI payment/settlement	HOLD until G4 receipt verifier
Custom resale PCB	HOLD until G1 + G2 logs

Final Call: GO for G1 USB-3 loopback; HOLD for product/custom PCB until G1/G2 pass.

---

13. Battle Cry

Coq anchors it. FPGA routes it. USB-3 feeds it. Mesh carries it. TRI pays only for receipts.

phi^2 + phi^-2 = 3 · TRINITY TERNARY INTERNET · NO LINUX IN THE CORE

[gHashTag]

✅ G0 closed — PR merged into main

Merge state (verified via GitHub API):

Field	Value
PR	tt-trinity-gf16#2
State	MERGED
Merged at	2026-05-13T15:06:02Z
Merged by	@gHashTag
Base	main
Squash merge SHA	65d2a60
Squash title	feat: Trinity v0 RTL mesh fabric (CPU-less, GF16 dot4 tiles) (#2)

Gate ledger update

Gate	Status
G0 — PR #2 placement / GDS / merge	✅ DONE (DPL-0036 fix shipped to main)
G1 — USB-3 loopback (sim)	✅ GREEN — 100/100 0x47C0 (sim/g1_loopback)
G1 — USB-3 loopback (silicon)	🟡 HOLD — needs QMTECH XC7A100T + FT601 board
G2 — Host packet tool (sim)	✅ GREEN — 100/100 receipts status=pass
G3 — Mesh adapter spec	✅ frozen (PHY HOLD per Rule 4)
G4 — Receipt verifier	✅ GREEN — 7/7 unit + 100/100 verified
G5 — Carrier board spec	✅ frozen (fab HOLD per §12)

Carried forward (out of TRI-NET-G1 scope)

• ICA-002 — test/tb.v:79 probes user_project.mesh_result[_valid] which synthesis flattens; gl_test post-GDS sim fails. Pre-existing in 702559b, only became visible because gds no longer blocks. Recommended follow-up PR: gate the hierarchical refs under \ifndef GL_TEST` or expose them as top-level outputs.

Next lane

L-DPC6 advances to silicon-G1: program merged main (65d2a60) bitstream onto QMTECH XC7A100T with FT601, reproduce the 100/100 0x47C0 loopback on real hardware. After silicon-G1: G3 two-node physical mesh exchange.

Anchor: phi^2 + phi^-2 = 3

[gHashTag]

🔧 silicon-G1 artefacts shipped — ready to flash on physical hardware

Подготовил всё для прошивки QMTECH XC7A100T + FT601, сам flash не делал — это шаг оператора на железе.

PR (artefacts only — no functional risk)

tt-trinity-gf16#9 — feat/silicon-g1, branched from main@65d2a60 (PR #2 squash merge).

Path	Purpose
boards/qmtech_a100t/build/build.tcl	Vivado non-project synth+impl+bitstream. Synth-time R2 gate (DSP48 = 0), timing gate (WNS ≥ 0).
boards/qmtech_a100t/build/Makefile	Targets bit, program, flash, silicon-g1, verify. Vivado for synth; openFPGALoader for upload.
host/silicon_g1_runner.py	ftd3xx 100× GF16 dot4 loopback → JSONL receipts. R5-honest refusal: exit 2 if no FT601 / no driver.
docs/boards/SILICON_G1_BRINGUP.md	Hardware list, tool list, run procedure, pre-registered acceptance gates SG1-01..SG1-08.

Pre-registered acceptance (frozen BEFORE first physical run)

Gate	Expected
SG1-01	Vivado DSP48 count = 0
SG1-02	Setup WNS ≥ 0 ns
SG1-03	DRC clean (no CRITICAL_WARNING)
SG1-04	Bitstream size 3..6 MB
SG1-05	lsusb shows FT601 (0403:601f / 601e)
SG1-06	silicon_g1_runner.py --jobs 100 → exit 0 + SILICON_G1_GATE_GREEN: 100/100 0x47C0
SG1-07	Ledger sha256 reproducible mod nonce/ts
SG1-08	Util grep MicroBlaze/AXI/LMB → 0 hits

ANY SG1-01..SG1-06 ❌ ⇒ H1 marked FALSIFIED for silicon lane.

R5 honesty — what we still do NOT claim

• No SILICON_G1_GREEN until a physical board produces a real ledger.
• No "DePIN node complete" — needs silicon-G3 (2 physical nodes exchange).
• No CI silicon-G1 run (no FT601 in GH Actions runners; CI only lints).

Operator next steps (offline / playRas)

1. Merge tt-trinity-gf16#9.

2. cd boards/qmtech_a100t/build
   make silicon-g1     # bit -> program -> verify -> verdict

3. Commit out/silicon_g1_receipts.jsonl + timing_summary.rpt + utilization.rpt to evidence dir.
4. NASA report TRI-NET-G1-RVR-002 with SG1-01..SG1-08 matrix.
5. After SG1 GREEN → silicon-G3 (2 nodes exchange one job + receipt via off-chip mesh).

Anchor: phi^2 + phi^-2 = 3

[gHashTag]

L-DPC6 silicon-G1 — autonomous loop status (TRI-NET-G1-RVR-002 follow-up)

Anchor: phi^2 + phi^-2 = 3 · Lane: L-DPC6 silicon-G1 · EPIC: #19

What just landed

• PR tt-trinity-gf16#9 — silicon-G1 bring-up (build.tcl, Makefile, host runner, BRINGUP.md, SG1-01..08) — MERGED at a423ed5, all 5 CI green (gds / precheck / gl_test / viewer / GitGuardian).
• PR tt-trinity-gf16#10 — silicon-G1 follow-up extending acceptance to PR deps: bump @docusaurus/theme-mermaid from 3.9.2 to 3.10.0 in /docs #6 receipts + PR 🎯 ONE SHOT: Phase 1 — Export IGLA Champion Weights to GF16 (refs #7) #8 Wave-26b SUPER-CROWN. OPEN.
• PR trios#784 — PhD monograph Ch.12 §4.5 silicon-G1 evidence + Table 12.SG1 pre-registered acceptance matrix. OPEN.

New pre-registered gates (frozen against tt-trinity-gf16@a423ed5)

Gate	Test	Expected
SG1-09	Receipt engine roundtrip (PR #6 TRN_OP_RECEIPT)	silicon_g1_runner.py --probe receipt --jobs 32 → 32/32 op=0x5 + 0x47C0 + echoed nonce LSBs
SG1-10	SUPER-CROWN 8×2 tile coverage (PR #8)	--probe supercrown --jobs 16 rotates tile_id ∈ {0..15}, each returns 0x47C0 to correct dst
SG1-11	16k-gate timing on QMTECH	post-route DCP report_timing_summary WNS ≥ 0 ns at 50 MHz and 100 MHz with full SUPER-CROWN + receipt engine

Base suite SG1-01..08 (frozen against 65d2a60) is unchanged. Extension suite SG1-09..11 (frozen against a423ed5) covers what main actually contains today.

R5-honesty preserved

Runner still exits 2 + REFUSAL banner + writes no ledger when ftd3xx missing or no FT60x on USB. Verified locally for --probe receipt --jobs 1 and --probe supercrown --jobs 1. No GATE_GREEN line is reachable without a real device.

What stays in your hands

1. cd boards/qmtech_a100t/build && make bit on the bench (Vivado).
2. make program to flash QMTECH XC7A100T via JTAG.
3. Three probe runs:

   python3 host/silicon_g1_runner.py --probe dot4       --jobs 100 --out ledger_sg1_06.jsonl
   python3 host/silicon_g1_runner.py --probe receipt    --jobs 32  --out ledger_sg1_09.jsonl
   python3 host/silicon_g1_runner.py --probe supercrown --jobs 16  --out ledger_sg1_10.jsonl

4. Three GATE_GREEN lines + three JSONL ledgers → I write TRI-NET-G1-RVR-002 NASA report from your bench output.

Forward-looking: L-DPC7 Wave-7 pre-registration draft

docs/missions/L-DPC7_WAVE7_ONESHOT.md (in PR #10) stakes out the post-defense TTIHP27a tape-out: 8 modules L-S20..L-S27, ~27.5k gates on IHP SG13G2, split into Wave 7a (Q3 2026) and Wave 7b (Q4 2026), KOSCHEI ISA freeze as hard prerequisite, Coq witness mapping pre-defense, no JEPA / no Hailo / no Axelera language until on-bench chip-in-hand. Not a flight-cleared issue yet — explicit DRAFT.

Defense scope honest cut

Pre-defense (2026-06-15): silicon-G1 GREEN on FPGA → TRL-4 measured evidence + Ch.12 §4.5 in monograph. Post-defense roadmap: TTIHP27a tape-out → chip-in-hand 2026-12-16. The dissertation does not claim ASIC silicon evidence pre-defense.

[gHashTag]

🔥 IGNITE — L-DPC7 Wave-7 TTIHP27a (post-defense ASIC roadmap)

Anchor: φ² + φ⁻² = 3 · Lane: L-DPC7 · Parent EPIC: trinity-fpga#19 · Issue: trinity-fpga#50

A new pre-registration ONE SHOT just opened on the Trinity hardware strand. Status is DRAFT — Coq witnesses and KOSCHEI ISA freeze are hard prerequisites before any L-S2x RTL PR opens.

TL;DR

• 8 synthesizable modules L-S20..L-S27 on TTIHP27a (IHP SG13G2, 130 nm, Q4 2026)
• Split into Wave 7a (Q3 2026, ~15.5k gates) and Wave 7b (Q4 2026, ~12k gates)
• 8 pre-registered gates TTIHP-G1..G8, frozen pre-merge
• No "JEPA on silicon" / no "Hailo competitor" / no "Axelera competitor" until 2026-12-16 chip-in-hand

Hard prerequisites BEFORE 7a opens

1. silicon-G1 GREEN on QMTECH XC7A100T+FT601 (closes trinity-fpga#48)
2. KOSCHEI ISA v0.1 sha256-frozen in trinity-clara/spec/koschei/ISA-v0.1.md

Defense scope discipline

The PhD defense 2026-06-15 narrative is FPGA-validated TRL-4 (via silicon-G1) + ASIC tape-out funded post-defense roadmap. The dissertation explicitly does NOT claim ASIC silicon evidence pre-defense (cf trios PR #784 Ch.12 §4.5).

Claim protocol

Comment on trinity-fpga#50:

• 🛡️ claim L-S2x @ <agent-id> — one agent per module
• Heartbeat every 4 hours with commit SHA + Yosys gate count
• 🔓 lane released after > 4h silence (watchdog)

Related artefacts

• silicon-G1 base (merged): tt-trinity-gf16#9 at a423ed5
• silicon-G1 extension SG1-09..11 + L-DPC7 draft: tt-trinity-gf16#10
• PhD Ch.12 §4.5 silicon-G1 evidence: trios#784
• TRI-1 SKU repos (PETAL): tt-trinity-nano · tt-trinity-max

— Queen of the Hive · spark v1.1 three-thread protocol