Add a RISC-V target to the embedded smoke tests

[kmolan]

Run the existing smoke checks in tools/embedded-smoke on riscv32imc-unknown-none-elf (the ESP32-C3 class of parts), the first non-ARM bare-metal target. The Cortex-M harness does not carry over: this needs riscv-rt and RISC-V semihosting in place of cortex-m-rt/cortex-m-semihosting, a memory map for the QEMU virt machine (qemu-system-riscv32), and the target wired into build.rs, the CI matrix, and ci/budgets.toml. The checks in src/checks.rs run unchanged.

Done when: all four checks pass under QEMU with the same known answers as the ARM targets, and the target is gated in CI with its own flash/stack budgets.

[rtmongold]

working on this, unless someone comes along that really wants it.

[kmolan]

@rtmongold feel free to continue working on this, but beware that I am in the middle of an architecture refactor for this module. I am trying to consolidate all our QA layers so its more scalable, and less confusing to maintain in future.

[rtmongold]

@kmolan I opened a draft PR with the work I have done, so you can look it over. I still have more work to do around the documentation. I can also leave this as a draft and rebase off your work when you are ready.