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Vadim Fedorenkokubalewski
Vadim Fedorenko
authored and
kubalewski
committed
dpll: api header: Add DPLL framework base functions
DPLL framework is used to represent and configure DPLL devices in systems. Each device that has DPLL and can configure sources and outputs can use this framework. Netlink interface is used to provide configuration data and to receive notification messages about changes in the configuration or status of DPLL device. Inputs and outputs of the DPLL device are represented as special objects which could be dynamically added to and removed from DPLL device. Add kernel api header, make dpll subsystem available to device drivers. Add/update makefiles/Kconfig to allow compilation of dpll subsystem. v9->v10: - add phase-shift, pin-phase-adjust attributes Co-developed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Milena Olech <milena.olech@intel.com> Co-developed-by: Michal Michalik <michal.michalik@intel.com> Signed-off-by: Michal Michalik <michal.michalik@intel.com> Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Co-developed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
1 parent 27bd586 commit e95421d

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‎MAINTAINERS‎

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@@ -6307,6 +6307,14 @@ F: Documentation/networking/device_drivers/ethernet/freescale/dpaa2/switch-drive
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F: drivers/net/ethernet/freescale/dpaa2/dpaa2-switch*
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F: drivers/net/ethernet/freescale/dpaa2/dpsw*
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DPLL CLOCK SUBSYSTEM
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M: Vadim Fedorenko <vadfed@fb.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/dpll/*
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F: include/net/dpll.h
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F: include/uapi/linux/dpll.h
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DRBD DRIVER
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M: Philipp Reisner <philipp.reisner@linbit.com>
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M: Lars Ellenberg <lars.ellenberg@linbit.com>

‎drivers/Kconfig‎

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@@ -243,4 +243,6 @@ source "drivers/hte/Kconfig"
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source "drivers/cdx/Kconfig"
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source "drivers/dpll/Kconfig"
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endmenu

‎drivers/Makefile‎

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@@ -195,3 +195,4 @@ obj-$(CONFIG_PECI) += peci/
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obj-$(CONFIG_HTE) += hte/
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obj-$(CONFIG_DRM_ACCEL) += accel/
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obj-$(CONFIG_CDX_BUS) += cdx/
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obj-$(CONFIG_DPLL) += dpll/

‎drivers/dpll/Kconfig‎

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Generic DPLL drivers configuration
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#
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config DPLL
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bool

‎drivers/dpll/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for DPLL drivers.
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#
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obj-$(CONFIG_DPLL) += dpll.o
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dpll-y += dpll_core.o
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dpll-y += dpll_netlink.o
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dpll-y += dpll_nl.o

‎include/linux/dpll.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Meta Platforms, Inc. and affiliates
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* Copyright (c) 2023 Intel and affiliates
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*/
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#ifndef __DPLL_H__
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#define __DPLL_H__
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#include <uapi/linux/dpll.h>
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#include <linux/device.h>
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#include <linux/netlink.h>
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struct dpll_device;
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struct dpll_pin;
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struct dpll_device_ops {
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int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_mode *mode, struct netlink_ext_ack *extack);
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int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
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const enum dpll_mode mode,
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struct netlink_ext_ack *extack);
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bool (*mode_supported)(const struct dpll_device *dpll, void *dpll_priv,
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const enum dpll_mode mode,
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struct netlink_ext_ack *extack);
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int (*source_pin_idx_get)(const struct dpll_device *dpll,
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void *dpll_priv,
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u32 *pin_idx,
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struct netlink_ext_ack *extack);
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int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_lock_status *status,
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struct netlink_ext_ack *extack);
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int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
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s32 *temp, struct netlink_ext_ack *extack);
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int (*phase_shift_get)(const struct dpll_device *dpll, void *dpll_priv,
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s32 *phase_shift,
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struct netlink_ext_ack *extack);
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};
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struct dpll_pin_ops {
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int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const u64 frequency,
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struct netlink_ext_ack *extack);
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int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u64 *frequency, struct netlink_ext_ack *extack);
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int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const enum dpll_pin_direction direction,
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struct netlink_ext_ack *extack);
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int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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enum dpll_pin_direction *direction,
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struct netlink_ext_ack *extack);
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int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_pin *parent_pin,
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void *parent_pin_priv,
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enum dpll_pin_state *state,
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struct netlink_ext_ack *extack);
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int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv, enum dpll_pin_state *state,
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struct netlink_ext_ack *extack);
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int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_pin *parent_pin,
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void *parent_pin_priv,
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const enum dpll_pin_state state,
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struct netlink_ext_ack *extack);
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int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv,
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const enum dpll_pin_state state,
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struct netlink_ext_ack *extack);
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int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u32 *prio, struct netlink_ext_ack *extack);
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int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const u32 prio, struct netlink_ext_ack *extack);
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int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 *phase_adjust,
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struct netlink_ext_ack *extack);
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int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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const s32 phase_adjust,
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struct netlink_ext_ack *extack);
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};
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struct dpll_pin_frequency {
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u64 min;
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u64 max;
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};
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#define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
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{ \
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.min = _min, \
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.max = _max, \
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}
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#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
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#define DPLL_PIN_FREQUENCY_1PPS \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
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#define DPLL_PIN_FREQUENCY_10MHZ \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
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#define DPLL_PIN_FREQUENCY_IRIG_B \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
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#define DPLL_PIN_FREQUENCY_DCF77 \
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DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
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struct dpll_pin_phase_adjust_range {
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s32 min;
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s32 max;
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};
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struct dpll_pin_properties {
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const char *board_label;
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const char *panel_label;
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const char *package_label;
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enum dpll_pin_type type;
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unsigned long capabilities;
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u32 freq_supported_num;
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struct dpll_pin_frequency *freq_supported;
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struct dpll_pin_phase_adjust_range phase_range;
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};
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struct dpll_device
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*dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
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void dpll_device_put(struct dpll_device *dpll);
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int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
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const struct dpll_device_ops *ops, void *priv);
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void dpll_device_unregister(struct dpll_device *dpll,
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const struct dpll_device_ops *ops, void *priv);
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struct dpll_pin
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*dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
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const struct dpll_pin_properties *prop);
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int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_put(struct dpll_pin *pin);
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int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
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const struct dpll_pin_ops *ops, void *priv);
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int dpll_device_change_ntf(struct dpll_device *dpll);
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int dpll_pin_change_ntf(struct dpll_pin *pin);
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#endif

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