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Stanislav Fomichevkuba-moo
Stanislav Fomichev
authored and
kuba-moo
committed
ynl-gen-cpp: don't use c-style initializers for ynl_policy_attr
More strict/old compilers do not like them: error: designator order for field ‘ynl_policy_attr::type’ does not match declaration order in ‘ynl_policy_attr’ error: designator order for field ‘ynl_policy_attr::type’ does not match declaration order in ‘ynl_policy_attr Signed-off-by: Stanislav Fomichev <stfomichev@gmail.com>
1 parent d9923a1 commit 2a1d11f

12 files changed

Lines changed: 1373 additions & 650 deletions

‎generated/dpll-user.cpp‎

Lines changed: 102 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -183,8 +183,10 @@ std::string_view dpll_pin_capabilities_str(dpll_pin_capabilities value)
183183
/* Policies */
184184
static std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> dpll_frequency_range_policy = []() {
185185
std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> arr{};
186-
arr[DPLL_A_PIN_FREQUENCY_MIN] = { .name = "frequency-min", .type = YNL_PT_U64, };
187-
arr[DPLL_A_PIN_FREQUENCY_MAX] = { .name = "frequency-max", .type = YNL_PT_U64, };
186+
arr[DPLL_A_PIN_FREQUENCY_MIN].name = "frequency-min";
187+
arr[DPLL_A_PIN_FREQUENCY_MIN].type = YNL_PT_U64;
188+
arr[DPLL_A_PIN_FREQUENCY_MAX].name = "frequency-max";
189+
arr[DPLL_A_PIN_FREQUENCY_MAX].type = YNL_PT_U64;
188190
return arr;
189191
} ();
190192

@@ -195,11 +197,16 @@ struct ynl_policy_nest dpll_frequency_range_nest = {
195197

196198
static std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> dpll_pin_parent_device_policy = []() {
197199
std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> arr{};
198-
arr[DPLL_A_PIN_PARENT_ID] = { .name = "parent-id", .type = YNL_PT_U32, };
199-
arr[DPLL_A_PIN_DIRECTION] = { .name = "direction", .type = YNL_PT_U32, };
200-
arr[DPLL_A_PIN_PRIO] = { .name = "prio", .type = YNL_PT_U32, };
201-
arr[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, };
202-
arr[DPLL_A_PIN_PHASE_OFFSET] = { .name = "phase-offset", .type = YNL_PT_U64, };
200+
arr[DPLL_A_PIN_PARENT_ID].name = "parent-id";
201+
arr[DPLL_A_PIN_PARENT_ID].type = YNL_PT_U32;
202+
arr[DPLL_A_PIN_DIRECTION].name = "direction";
203+
arr[DPLL_A_PIN_DIRECTION].type = YNL_PT_U32;
204+
arr[DPLL_A_PIN_PRIO].name = "prio";
205+
arr[DPLL_A_PIN_PRIO].type = YNL_PT_U32;
206+
arr[DPLL_A_PIN_STATE].name = "state";
207+
arr[DPLL_A_PIN_STATE].type = YNL_PT_U32;
208+
arr[DPLL_A_PIN_PHASE_OFFSET].name = "phase-offset";
209+
arr[DPLL_A_PIN_PHASE_OFFSET].type = YNL_PT_U64;
203210
return arr;
204211
} ();
205212

@@ -210,8 +217,10 @@ struct ynl_policy_nest dpll_pin_parent_device_nest = {
210217

211218
static std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> dpll_pin_parent_pin_policy = []() {
212219
std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> arr{};
213-
arr[DPLL_A_PIN_PARENT_ID] = { .name = "parent-id", .type = YNL_PT_U32, };
214-
arr[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, };
220+
arr[DPLL_A_PIN_PARENT_ID].name = "parent-id";
221+
arr[DPLL_A_PIN_PARENT_ID].type = YNL_PT_U32;
222+
arr[DPLL_A_PIN_STATE].name = "state";
223+
arr[DPLL_A_PIN_STATE].type = YNL_PT_U32;
215224
return arr;
216225
} ();
217226

@@ -222,17 +231,28 @@ struct ynl_policy_nest dpll_pin_parent_pin_nest = {
222231

223232
static std::array<ynl_policy_attr,DPLL_A_MAX + 1> dpll_policy = []() {
224233
std::array<ynl_policy_attr,DPLL_A_MAX + 1> arr{};
225-
arr[DPLL_A_ID] = { .name = "id", .type = YNL_PT_U32, };
226-
arr[DPLL_A_MODULE_NAME] = { .name = "module-name", .type = YNL_PT_NUL_STR, };
227-
arr[DPLL_A_PAD] = { .name = "pad", .type = YNL_PT_IGNORE, };
228-
arr[DPLL_A_CLOCK_ID] = { .name = "clock-id", .type = YNL_PT_U64, };
229-
arr[DPLL_A_MODE] = { .name = "mode", .type = YNL_PT_U32, };
230-
arr[DPLL_A_MODE_SUPPORTED] = { .name = "mode-supported", .type = YNL_PT_U32, };
231-
arr[DPLL_A_LOCK_STATUS] = { .name = "lock-status", .type = YNL_PT_U32, };
232-
arr[DPLL_A_TEMP] = { .name = "temp", .type = YNL_PT_U32, };
233-
arr[DPLL_A_TYPE] = { .name = "type", .type = YNL_PT_U32, };
234-
arr[DPLL_A_LOCK_STATUS_ERROR] = { .name = "lock-status-error", .type = YNL_PT_U32, };
235-
arr[DPLL_A_CLOCK_QUALITY_LEVEL] = { .name = "clock-quality-level", .type = YNL_PT_U32, };
234+
arr[DPLL_A_ID].name = "id";
235+
arr[DPLL_A_ID].type = YNL_PT_U32;
236+
arr[DPLL_A_MODULE_NAME].name = "module-name";
237+
arr[DPLL_A_MODULE_NAME].type = YNL_PT_NUL_STR;
238+
arr[DPLL_A_PAD].name = "pad";
239+
arr[DPLL_A_PAD].type = YNL_PT_IGNORE;
240+
arr[DPLL_A_CLOCK_ID].name = "clock-id";
241+
arr[DPLL_A_CLOCK_ID].type = YNL_PT_U64;
242+
arr[DPLL_A_MODE].name = "mode";
243+
arr[DPLL_A_MODE].type = YNL_PT_U32;
244+
arr[DPLL_A_MODE_SUPPORTED].name = "mode-supported";
245+
arr[DPLL_A_MODE_SUPPORTED].type = YNL_PT_U32;
246+
arr[DPLL_A_LOCK_STATUS].name = "lock-status";
247+
arr[DPLL_A_LOCK_STATUS].type = YNL_PT_U32;
248+
arr[DPLL_A_TEMP].name = "temp";
249+
arr[DPLL_A_TEMP].type = YNL_PT_U32;
250+
arr[DPLL_A_TYPE].name = "type";
251+
arr[DPLL_A_TYPE].type = YNL_PT_U32;
252+
arr[DPLL_A_LOCK_STATUS_ERROR].name = "lock-status-error";
253+
arr[DPLL_A_LOCK_STATUS_ERROR].type = YNL_PT_U32;
254+
arr[DPLL_A_CLOCK_QUALITY_LEVEL].name = "clock-quality-level";
255+
arr[DPLL_A_CLOCK_QUALITY_LEVEL].type = YNL_PT_U32;
236256
return arr;
237257
} ();
238258

@@ -243,33 +263,64 @@ struct ynl_policy_nest dpll_nest = {
243263

244264
static std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> dpll_pin_policy = []() {
245265
std::array<ynl_policy_attr,DPLL_A_PIN_MAX + 1> arr{};
246-
arr[DPLL_A_PIN_ID] = { .name = "id", .type = YNL_PT_U32, };
247-
arr[DPLL_A_PIN_PARENT_ID] = { .name = "parent-id", .type = YNL_PT_U32, };
248-
arr[DPLL_A_PIN_MODULE_NAME] = { .name = "module-name", .type = YNL_PT_NUL_STR, };
249-
arr[DPLL_A_PIN_PAD] = { .name = "pad", .type = YNL_PT_IGNORE, };
250-
arr[DPLL_A_PIN_CLOCK_ID] = { .name = "clock-id", .type = YNL_PT_U64, };
251-
arr[DPLL_A_PIN_BOARD_LABEL] = { .name = "board-label", .type = YNL_PT_NUL_STR, };
252-
arr[DPLL_A_PIN_PANEL_LABEL] = { .name = "panel-label", .type = YNL_PT_NUL_STR, };
253-
arr[DPLL_A_PIN_PACKAGE_LABEL] = { .name = "package-label", .type = YNL_PT_NUL_STR, };
254-
arr[DPLL_A_PIN_TYPE] = { .name = "type", .type = YNL_PT_U32, };
255-
arr[DPLL_A_PIN_DIRECTION] = { .name = "direction", .type = YNL_PT_U32, };
256-
arr[DPLL_A_PIN_FREQUENCY] = { .name = "frequency", .type = YNL_PT_U64, };
257-
arr[DPLL_A_PIN_FREQUENCY_SUPPORTED] = { .name = "frequency-supported", .type = YNL_PT_NEST, .nest = &dpll_frequency_range_nest, };
258-
arr[DPLL_A_PIN_FREQUENCY_MIN] = { .name = "frequency-min", .type = YNL_PT_U64, };
259-
arr[DPLL_A_PIN_FREQUENCY_MAX] = { .name = "frequency-max", .type = YNL_PT_U64, };
260-
arr[DPLL_A_PIN_PRIO] = { .name = "prio", .type = YNL_PT_U32, };
261-
arr[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, };
262-
arr[DPLL_A_PIN_CAPABILITIES] = { .name = "capabilities", .type = YNL_PT_U32, };
263-
arr[DPLL_A_PIN_PARENT_DEVICE] = { .name = "parent-device", .type = YNL_PT_NEST, .nest = &dpll_pin_parent_device_nest, };
264-
arr[DPLL_A_PIN_PARENT_PIN] = { .name = "parent-pin", .type = YNL_PT_NEST, .nest = &dpll_pin_parent_pin_nest, };
265-
arr[DPLL_A_PIN_PHASE_ADJUST_MIN] = { .name = "phase-adjust-min", .type = YNL_PT_U32, };
266-
arr[DPLL_A_PIN_PHASE_ADJUST_MAX] = { .name = "phase-adjust-max", .type = YNL_PT_U32, };
267-
arr[DPLL_A_PIN_PHASE_ADJUST] = { .name = "phase-adjust", .type = YNL_PT_U32, };
268-
arr[DPLL_A_PIN_PHASE_OFFSET] = { .name = "phase-offset", .type = YNL_PT_U64, };
269-
arr[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET] = { .name = "fractional-frequency-offset", .type = YNL_PT_UINT, };
270-
arr[DPLL_A_PIN_ESYNC_FREQUENCY] = { .name = "esync-frequency", .type = YNL_PT_U64, };
271-
arr[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED] = { .name = "esync-frequency-supported", .type = YNL_PT_NEST, .nest = &dpll_frequency_range_nest, };
272-
arr[DPLL_A_PIN_ESYNC_PULSE] = { .name = "esync-pulse", .type = YNL_PT_U32, };
266+
arr[DPLL_A_PIN_ID].name = "id";
267+
arr[DPLL_A_PIN_ID].type = YNL_PT_U32;
268+
arr[DPLL_A_PIN_PARENT_ID].name = "parent-id";
269+
arr[DPLL_A_PIN_PARENT_ID].type = YNL_PT_U32;
270+
arr[DPLL_A_PIN_MODULE_NAME].name = "module-name";
271+
arr[DPLL_A_PIN_MODULE_NAME].type = YNL_PT_NUL_STR;
272+
arr[DPLL_A_PIN_PAD].name = "pad";
273+
arr[DPLL_A_PIN_PAD].type = YNL_PT_IGNORE;
274+
arr[DPLL_A_PIN_CLOCK_ID].name = "clock-id";
275+
arr[DPLL_A_PIN_CLOCK_ID].type = YNL_PT_U64;
276+
arr[DPLL_A_PIN_BOARD_LABEL].name = "board-label";
277+
arr[DPLL_A_PIN_BOARD_LABEL].type = YNL_PT_NUL_STR;
278+
arr[DPLL_A_PIN_PANEL_LABEL].name = "panel-label";
279+
arr[DPLL_A_PIN_PANEL_LABEL].type = YNL_PT_NUL_STR;
280+
arr[DPLL_A_PIN_PACKAGE_LABEL].name = "package-label";
281+
arr[DPLL_A_PIN_PACKAGE_LABEL].type = YNL_PT_NUL_STR;
282+
arr[DPLL_A_PIN_TYPE].name = "type";
283+
arr[DPLL_A_PIN_TYPE].type = YNL_PT_U32;
284+
arr[DPLL_A_PIN_DIRECTION].name = "direction";
285+
arr[DPLL_A_PIN_DIRECTION].type = YNL_PT_U32;
286+
arr[DPLL_A_PIN_FREQUENCY].name = "frequency";
287+
arr[DPLL_A_PIN_FREQUENCY].type = YNL_PT_U64;
288+
arr[DPLL_A_PIN_FREQUENCY_SUPPORTED].name = "frequency-supported";
289+
arr[DPLL_A_PIN_FREQUENCY_SUPPORTED].type = YNL_PT_NEST;
290+
arr[DPLL_A_PIN_FREQUENCY_SUPPORTED].nest = &dpll_frequency_range_nest;
291+
arr[DPLL_A_PIN_FREQUENCY_MIN].name = "frequency-min";
292+
arr[DPLL_A_PIN_FREQUENCY_MIN].type = YNL_PT_U64;
293+
arr[DPLL_A_PIN_FREQUENCY_MAX].name = "frequency-max";
294+
arr[DPLL_A_PIN_FREQUENCY_MAX].type = YNL_PT_U64;
295+
arr[DPLL_A_PIN_PRIO].name = "prio";
296+
arr[DPLL_A_PIN_PRIO].type = YNL_PT_U32;
297+
arr[DPLL_A_PIN_STATE].name = "state";
298+
arr[DPLL_A_PIN_STATE].type = YNL_PT_U32;
299+
arr[DPLL_A_PIN_CAPABILITIES].name = "capabilities";
300+
arr[DPLL_A_PIN_CAPABILITIES].type = YNL_PT_U32;
301+
arr[DPLL_A_PIN_PARENT_DEVICE].name = "parent-device";
302+
arr[DPLL_A_PIN_PARENT_DEVICE].type = YNL_PT_NEST;
303+
arr[DPLL_A_PIN_PARENT_DEVICE].nest = &dpll_pin_parent_device_nest;
304+
arr[DPLL_A_PIN_PARENT_PIN].name = "parent-pin";
305+
arr[DPLL_A_PIN_PARENT_PIN].type = YNL_PT_NEST;
306+
arr[DPLL_A_PIN_PARENT_PIN].nest = &dpll_pin_parent_pin_nest;
307+
arr[DPLL_A_PIN_PHASE_ADJUST_MIN].name = "phase-adjust-min";
308+
arr[DPLL_A_PIN_PHASE_ADJUST_MIN].type = YNL_PT_U32;
309+
arr[DPLL_A_PIN_PHASE_ADJUST_MAX].name = "phase-adjust-max";
310+
arr[DPLL_A_PIN_PHASE_ADJUST_MAX].type = YNL_PT_U32;
311+
arr[DPLL_A_PIN_PHASE_ADJUST].name = "phase-adjust";
312+
arr[DPLL_A_PIN_PHASE_ADJUST].type = YNL_PT_U32;
313+
arr[DPLL_A_PIN_PHASE_OFFSET].name = "phase-offset";
314+
arr[DPLL_A_PIN_PHASE_OFFSET].type = YNL_PT_U64;
315+
arr[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET].name = "fractional-frequency-offset";
316+
arr[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET].type = YNL_PT_UINT;
317+
arr[DPLL_A_PIN_ESYNC_FREQUENCY].name = "esync-frequency";
318+
arr[DPLL_A_PIN_ESYNC_FREQUENCY].type = YNL_PT_U64;
319+
arr[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED].name = "esync-frequency-supported";
320+
arr[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED].type = YNL_PT_NEST;
321+
arr[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED].nest = &dpll_frequency_range_nest;
322+
arr[DPLL_A_PIN_ESYNC_PULSE].name = "esync-pulse";
323+
arr[DPLL_A_PIN_ESYNC_PULSE].type = YNL_PT_U32;
273324
return arr;
274325
} ();
275326

@@ -475,7 +526,7 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
475526
} else if (type == DPLL_A_MODULE_NAME) {
476527
if (ynl_attr_validate(yarg, attr))
477528
return YNL_PARSE_CB_ERROR;
478-
dst->module_name.assign(ynl_attr_get_str(attr), ynl_attr_data_len(attr));
529+
dst->module_name.assign(ynl_attr_get_str(attr));
479530
} else if (type == DPLL_A_MODE) {
480531
if (ynl_attr_validate(yarg, attr))
481532
return YNL_PARSE_CB_ERROR;
@@ -689,15 +740,15 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
689740
} else if (type == DPLL_A_PIN_BOARD_LABEL) {
690741
if (ynl_attr_validate(yarg, attr))
691742
return YNL_PARSE_CB_ERROR;
692-
dst->board_label.assign(ynl_attr_get_str(attr), ynl_attr_data_len(attr));
743+
dst->board_label.assign(ynl_attr_get_str(attr));
693744
} else if (type == DPLL_A_PIN_PANEL_LABEL) {
694745
if (ynl_attr_validate(yarg, attr))
695746
return YNL_PARSE_CB_ERROR;
696-
dst->panel_label.assign(ynl_attr_get_str(attr), ynl_attr_data_len(attr));
747+
dst->panel_label.assign(ynl_attr_get_str(attr));
697748
} else if (type == DPLL_A_PIN_PACKAGE_LABEL) {
698749
if (ynl_attr_validate(yarg, attr))
699750
return YNL_PARSE_CB_ERROR;
700-
dst->package_label.assign(ynl_attr_get_str(attr), ynl_attr_data_len(attr));
751+
dst->package_label.assign(ynl_attr_get_str(attr));
701752
} else if (type == DPLL_A_PIN_TYPE) {
702753
if (ynl_attr_validate(yarg, attr))
703754
return YNL_PARSE_CB_ERROR;

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