@@ -54,6 +54,9 @@ static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
5454 unsigned int regval = ucontrol -> value .integer .value [0 ];
5555 int ret ;
5656
57+ if (regval < EASRC_WIDTH_16_BIT || regval > EASRC_WIDTH_24_BIT )
58+ return - EINVAL ;
59+
5760 ret = (easrc_priv -> bps_iec958 [mc -> regbase ] != regval );
5861
5962 easrc_priv -> bps_iec958 [mc -> regbase ] = regval ;
@@ -70,8 +73,16 @@ static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
7073 struct soc_mreg_control * mc =
7174 (struct soc_mreg_control * )kcontrol -> private_value ;
7275
73- ucontrol -> value .enumerated .item [0 ] = easrc_priv -> bps_iec958 [mc -> regbase ];
76+ ucontrol -> value .integer .value [0 ] = easrc_priv -> bps_iec958 [mc -> regbase ];
77+
78+ return 0 ;
79+ }
7480
81+ static int fsl_easrc_iec958_info (struct snd_kcontrol * kcontrol ,
82+ struct snd_ctl_elem_info * uinfo )
83+ {
84+ uinfo -> type = SNDRV_CTL_ELEM_TYPE_IEC958 ;
85+ uinfo -> count = 1 ;
7586 return 0 ;
7687}
7788
@@ -81,11 +92,33 @@ static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
8192 struct snd_soc_component * component = snd_kcontrol_chip (kcontrol );
8293 struct soc_mreg_control * mc =
8394 (struct soc_mreg_control * )kcontrol -> private_value ;
84- unsigned int regval ;
95+ struct fsl_asrc * easrc = snd_soc_component_get_drvdata (component );
96+ unsigned int * regval = (unsigned int * )ucontrol -> value .iec958 .status ;
97+ int ret ;
98+
99+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS0 (mc -> regbase ), & regval [0 ]);
100+ if (ret )
101+ return ret ;
102+
103+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS1 (mc -> regbase ), & regval [1 ]);
104+ if (ret )
105+ return ret ;
106+
107+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS2 (mc -> regbase ), & regval [2 ]);
108+ if (ret )
109+ return ret ;
110+
111+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS3 (mc -> regbase ), & regval [3 ]);
112+ if (ret )
113+ return ret ;
85114
86- regval = snd_soc_component_read (component , mc -> regbase );
115+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS4 (mc -> regbase ), & regval [4 ]);
116+ if (ret )
117+ return ret ;
87118
88- ucontrol -> value .integer .value [0 ] = regval ;
119+ ret = regmap_read (easrc -> regmap , REG_EASRC_CS5 (mc -> regbase ), & regval [5 ]);
120+ if (ret )
121+ return ret ;
89122
90123 return 0 ;
91124}
@@ -97,22 +130,52 @@ static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
97130 struct soc_mreg_control * mc =
98131 (struct soc_mreg_control * )kcontrol -> private_value ;
99132 struct fsl_asrc * easrc = snd_soc_component_get_drvdata (component );
100- unsigned int regval = ucontrol -> value .integer .value [0 ];
101- bool changed ;
133+ unsigned int * regval = (unsigned int * )ucontrol -> value .iec958 .status ;
102134 int ret ;
103135
104- ret = regmap_update_bits_check (easrc -> regmap , mc -> regbase ,
105- GENMASK (31 , 0 ), regval , & changed );
106- if (ret != 0 )
136+ ret = pm_runtime_resume_and_get (component -> dev );
137+ if (ret )
107138 return ret ;
108139
109- return changed ;
140+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS0 (mc -> regbase ),
141+ GENMASK (31 , 0 ), regval [0 ]);
142+ if (ret != 0 )
143+ goto err ;
144+
145+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS1 (mc -> regbase ),
146+ GENMASK (31 , 0 ), regval [1 ]);
147+ if (ret != 0 )
148+ goto err ;
149+
150+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS2 (mc -> regbase ),
151+ GENMASK (31 , 0 ), regval [2 ]);
152+ if (ret != 0 )
153+ goto err ;
154+
155+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS3 (mc -> regbase ),
156+ GENMASK (31 , 0 ), regval [3 ]);
157+ if (ret != 0 )
158+ goto err ;
159+
160+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS4 (mc -> regbase ),
161+ GENMASK (31 , 0 ), regval [4 ]);
162+ if (ret != 0 )
163+ goto err ;
164+
165+ ret = regmap_update_bits (easrc -> regmap , REG_EASRC_CS5 (mc -> regbase ),
166+ GENMASK (31 , 0 ), regval [5 ]);
167+ if (ret != 0 )
168+ goto err ;
169+ err :
170+ pm_runtime_put_autosuspend (component -> dev );
171+
172+ return ret ;
110173}
111174
112175#define SOC_SINGLE_REG_RW (xname , xreg ) \
113176{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
114177 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
115- .info = snd_soc_info_xr_sx , .get = fsl_easrc_get_reg, \
178+ .info = fsl_easrc_iec958_info , .get = fsl_easrc_get_reg, \
116179 .put = fsl_easrc_set_reg, \
117180 .private_value = (unsigned long)&(struct soc_mreg_control) \
118181 { .regbase = xreg, .regcount = 1, .nbits = 32, \
@@ -143,30 +206,10 @@ static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
143206 SOC_SINGLE_VAL_RW ("Context 2 IEC958 Bits Per Sample" , 2 ),
144207 SOC_SINGLE_VAL_RW ("Context 3 IEC958 Bits Per Sample" , 3 ),
145208
146- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS0" , REG_EASRC_CS0 (0 )),
147- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS0" , REG_EASRC_CS0 (1 )),
148- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS0" , REG_EASRC_CS0 (2 )),
149- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS0" , REG_EASRC_CS0 (3 )),
150- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS1" , REG_EASRC_CS1 (0 )),
151- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS1" , REG_EASRC_CS1 (1 )),
152- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS1" , REG_EASRC_CS1 (2 )),
153- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS1" , REG_EASRC_CS1 (3 )),
154- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS2" , REG_EASRC_CS2 (0 )),
155- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS2" , REG_EASRC_CS2 (1 )),
156- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS2" , REG_EASRC_CS2 (2 )),
157- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS2" , REG_EASRC_CS2 (3 )),
158- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS3" , REG_EASRC_CS3 (0 )),
159- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS3" , REG_EASRC_CS3 (1 )),
160- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS3" , REG_EASRC_CS3 (2 )),
161- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS3" , REG_EASRC_CS3 (3 )),
162- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS4" , REG_EASRC_CS4 (0 )),
163- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS4" , REG_EASRC_CS4 (1 )),
164- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS4" , REG_EASRC_CS4 (2 )),
165- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS4" , REG_EASRC_CS4 (3 )),
166- SOC_SINGLE_REG_RW ("Context 0 IEC958 CS5" , REG_EASRC_CS5 (0 )),
167- SOC_SINGLE_REG_RW ("Context 1 IEC958 CS5" , REG_EASRC_CS5 (1 )),
168- SOC_SINGLE_REG_RW ("Context 2 IEC958 CS5" , REG_EASRC_CS5 (2 )),
169- SOC_SINGLE_REG_RW ("Context 3 IEC958 CS5" , REG_EASRC_CS5 (3 )),
209+ SOC_SINGLE_REG_RW ("Context 0 IEC958 CS" , 0 ),
210+ SOC_SINGLE_REG_RW ("Context 1 IEC958 CS" , 1 ),
211+ SOC_SINGLE_REG_RW ("Context 2 IEC958 CS" , 2 ),
212+ SOC_SINGLE_REG_RW ("Context 3 IEC958 CS" , 3 ),
170213};
171214
172215/*
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