Technology-dependent primitives need to be swapped out according to the target (simulation, ASIC, Xilinx FPGA, Altera FPGA). There are three different techniques used in this repo to accomplish this in different places:
- `define Macros with `ifdef statements
- SystemVerilog parameters with
generate if blocks
- FuseSoC virtual cores
(1) is used in ram_downsizer_w64_r8.sv and ram_upsizer_w8_r64.sv
(2) is used wherever parameter TARGET is given, in the MAC and the top level
(3) is used in the rest of the project
The latter is the preferred approach in other lowRISC projects and the least intrusive into the HDL, but implementing it will require some refactoring of legacy MAC code.
Technology-dependent primitives need to be swapped out according to the target (simulation, ASIC, Xilinx FPGA, Altera FPGA). There are three different techniques used in this repo to accomplish this in different places:
generate ifblocks(1) is used in
ram_downsizer_w64_r8.svandram_upsizer_w8_r64.sv(2) is used wherever
parameter TARGETis given, in the MAC and the top level(3) is used in the rest of the project
The latter is the preferred approach in other lowRISC projects and the least intrusive into the HDL, but implementing it will require some refactoring of legacy MAC code.