When linted with Verilator, the TARGET parameter (which is present on many modules) causes many WIDTHEXPAND warnings
Because no type is given, the parser infers an array of bytes. When the default value is "XILINX", it infers an array of 6 bytes. When a value of "SIM" is provided, this gives lots of inconsistent width errors.
%Warning-WIDTHEXPAND: src/lowrisc_ethernet_mac_0/oddr.sv:101:21: Operator EQ expects 48 bits on the LHS, but LHS's VARREF 'TARGET' generates 24 bits.
: ... note: In instance 'ethernet_top_axi_tb.dut.ethernet_top_inst.mac_wrapper_inst.rgmii_soc_inst.core_inst.eth_mac_inst.eth_mac_1g_rgmii_inst.rgmii_phy_if_inst.clk_oddr_inst'
101 | end else if (TARGET == "ALTERA") begin : gen_altera_target
| ^~
%Warning-WIDTHEXPAND: src/lowrisc_ethernet_mac_0/iddr.sv:68:12: Operator EQ expects 48 bits on the LHS, but LHS's VARREF 'TARGET' generates 24 bits.
: ... note: In instance 'ethernet_top_axi_tb.dut.ethernet_top_inst.mac_wrapper_inst.rgmii_soc_inst.core_inst.eth_mac_inst.eth_mac_1g_rgmii_inst.rgmii_phy_if_inst.rx_ssio_ddr_inst.data_iddr_inst'
68 | if (TARGET == "XILINX") begin : gen_xilinx_iddr
| ^~
When linted with Verilator, the
TARGETparameter (which is present on many modules) causes many WIDTHEXPAND warningsBecause no type is given, the parser infers an array of bytes. When the default value is "XILINX", it infers an array of 6 bytes. When a value of "SIM" is provided, this gives lots of inconsistent width errors.