sw: tests: add Verilator DRAM loading test

Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>

Author: ziuziakowska

sw/device/lib/boot/dram_test.ld

@@ -0,0 +1,90 @@
+/* Copyright lowRISC contributors (COSMIC project). */
+/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+OUTPUT_ARCH(riscv)
+
+INCLUDE memory.ld
+
+MEMORY {
+    ram (RWX) : ORIGIN = ORIGIN(DRAM), LENGTH = LENGTH(DRAM)
+}
+
+/* Provided in init_vectors.S, immediately jumps into _start. */
+ENTRY(_init_vector)
+
+SECTIONS {
+    _program_start = ORIGIN(ram);
+
+    .init_vectors ORIGIN(ram) : {
+        *(.init_vectors)
+    } > ram
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text.*)
+        . = ALIGN(8);
+    } > ram
+
+    .rodata : {
+        . = ALIGN(8);
+        /* Small rodata before large rodata */
+        *(.srodata)
+        *(.srodata.*)
+        *(.rodata)
+        *(.rodata.*)
+        . = ALIGN(8);
+    } > ram
+
+    /* capability relocation entries */
+    /* __start___cap_relocs and __stop___cap_relocs are provided by the toolchain */
+    __cap_relocs : {
+        *(__cap_relocs)
+        . = ALIGN(8);
+    } > ram
+
+    .data : {
+        . = ALIGN(8);
+        /* Small data before large data */
+        *(.sdata)
+        *(.sdata.*)
+        *(.data)
+        *(.data.*)
+        . = ALIGN(8);
+    } > ram
+
+    .bss : {
+        . = ALIGN(8);
+        _bss_start = .;
+        _sbss = .; /* Rust */
+        /* Small bss before large bss */
+        *(.sbss)
+        *(.sbss.*)
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        . = ALIGN(8);
+        _ebss = .; /* Rust */
+        _bss_end = .;
+    } > ram
+
+    .got : {
+        . = ALIGN(8);
+        *(.got)
+        *(.got.*)
+        . = ALIGN(8);
+    } > ram
+
+    . = ALIGN(1024);
+    .stack : {
+        . = ALIGN(1024);
+        _stack_bottom = .;
+        . = . + 1024;
+        _stack_top = .;
+        _stack_len = _stack_top - _stack_bottom;
+    } > ram
+
+    . = ALIGN(8);
+    _program_end = .;
+}

sw/device/tests/CMakeLists.txt

@@ -18,3 +18,5 @@ mocha_add_test(NAME tag_controller_tag_test SOURCES tag_controller/tag_test.c LI
 mocha_add_test(NAME timer_smoketest SOURCES timer/smoketest.c LIBRARIES ${LIBS} FPGA)
 mocha_add_test(NAME timer_interrupt_test SOURCES timer/interrupt.c LIBRARIES ${LIBS})
 mocha_add_test(NAME uart_smoketest SOURCES uart/smoketest.c LIBRARIES ${LIBS})
+
+add_subdirectory(dram)

sw/device/tests/dram/CMakeLists.txt

@@ -0,0 +1,46 @@
+# Copyright lowRISC contributors (COSMIC project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# This DRAM test is to test loading a binary into DRAM in Verilator,
+# before we have general support for running tests from DRAM.
+# For this test, we build a version of the test framework test linked at DRAM
+# which we load alongside the test binary. The test binary just jumps into DRAM.
+
+# TODO: This should be generalised to all tests once we have the ability to load
+# DRAM in all environments (FPGA, DV).
+
+set(LIBS hal runtime startup test_framework)
+
+add_executable(test_framework_test_vanilla_dram ../test_framework/smoketest.c)
+target_compile_options(test_framework_test_vanilla_dram PUBLIC ${VANILLA_FLAGS})
+foreach(LIB ${LIBS})
+    target_link_libraries(test_framework_test_vanilla_dram PUBLIC ${LIB}_vanilla)
+    target_include_directories(test_framework_test_vanilla_dram PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../../lib")
+endforeach()
+target_link_options(
+    test_framework_test_vanilla_dram PUBLIC
+    # Workaround: This address doesn't matter as we don't use system reset here,
+    # but it needs to be addressible by the medany code model.
+    "-Wl,--defsym,BOOT_ROM_OFFSET=0x80000000"
+    "-T" "dram_test.ld"
+    "-L" ${LDS_DIR}
+)
+
+add_executable(dram_test_rom ../dram/dram_test_rom.c)
+target_compile_options(dram_test_rom PUBLIC ${VANILLA_FLAGS})
+foreach(LIB ${LIBS})
+    target_link_libraries(dram_test_rom PUBLIC ${LIB}_vanilla)
+    target_include_directories(dram_test_rom PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../../lib")
+endforeach()
+target_link_options(
+    dram_test_rom PUBLIC
+    "-Wl,--defsym,BOOT_ROM_OFFSET=0x00"
+    "-T" "${LDS}"
+    "-L" ${LDS_DIR}
+)
+
+add_test(
+    NAME dram_load_test_sim_verilator
+    COMMAND ${PROJECT_SOURCE_DIR}/../util/verilator_runner.sh -E dram_test_rom -E test_framework_test_vanilla_dram
+)

sw/device/tests/dram/dram_test_rom.c

@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors (COSMIC project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "hal/mocha.h"
+#include "hal/uart.h"
+#include "runtime/print.h"
+#if defined(__riscv_zcherihybrid)
+#include <cheriintrin.h>
+#endif /* defined(__riscv_zcherihybrid) */
+
+// This test expects a test binary to be loaded into DRAM.
+// This will just jump to the start of that test.
+
+bool test_main(void)
+{
+    uart_t console = mocha_system_uart();
+    uart_init(console);
+
+    enum : uint64_t { boot_vector = dram_base + 0x80 };
+    uprintf(console, "jumping to DRAM boot vector: %lx\n", boot_vector);
+
+    void (*boot)(void) = (void (*)(void))boot_vector;
+    boot();
+
+    /* Test in DRAM should have succeeded and terminated the test */
+    return false;
+}