platform: tigerlake: remove use of SOF clock interface

Take benefit of the ability to build SOF Zephyr without SOF clock
interface and drop all the clock related definitions from TGL
platform code.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>

Author: kv2019i

src/platform/Kconfig

@@ -340,6 +340,7 @@ config CAVS
 	default n
 	select INTEL
 	select INTEL_MN
+	select SOF_ZEPHYR_NO_SOF_CLOCK
 
 config CAVS_VERSION_2_5
 	depends on CAVS

src/platform/intel/cavs/include/cavs/lib/clk.h

@@ -116,14 +116,12 @@ int platform_init(struct sof *sof)
 {
 	int ret;
 
-	trace_point(TRACE_BOOT_PLATFORM_CLOCK);
-	platform_clock_init(sof);
-
 	trace_point(TRACE_BOOT_PLATFORM_SCHED);
 	scheduler_init_edf();
 
 	/* init low latency timer domain and scheduler */
-	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK);
+	/* clk is ignored on Zephyr so pass 0 */
+	sof->platform_timer_domain = timer_domain_init(sof->platform_timer, 0);
 	scheduler_init_ll(sof->platform_timer_domain);
 
 	/* init the system agent */

src/platform/intel/cavs/platform.c

@@ -19,18 +19,11 @@
 #include <stddef.h>
 #include <stdint.h>
 
+#include <cavs/version.h>
+
 struct ll_schedule_domain;
 struct timer;
 
-/*! \def PLATFORM_DEFAULT_CLOCK
- *  \brief clock source for audio pipeline
- *
- *  There are two types of clock: cpu clock which is a internal clock in
- *  xtensa core, and ssp clock which is provided by external HW IP.
- *  The choice depends on HW features on different platform
- */
-#define PLATFORM_DEFAULT_CLOCK CLK_SSP
-
 /* Host page size */
 #define HOST_PAGE_SIZE		4096
 

src/platform/tigerlake/include/platform/lib/clk.h

@@ -222,8 +222,6 @@ if (CONFIG_SOC_SERIES_INTEL_CAVS_V25)
 	# Platform sources
 	zephyr_library_sources(
 		${SOF_PLATFORM_PATH}/intel/cavs/platform.c
-		${SOF_PLATFORM_PATH}/tigerlake/lib/clk.c
-		lib/clk.c
 		lib/dma.c
 	)