bus_design.tex

\section{Bus Design}
\label{sec:bus}
During normal operation, \bus remains in Bus~Idle~(\ref{sec:bus-idle}).
A transmission begins with Arbitration~(\ref{sec:bus-arbitration}), then
Message Transmission~(\ref{sec:bus-transmission}). The transmitter then
Interjects~(\ref{sec:bus-interjection}) the bus and indicates the complete
message was sent. During the Control~(\ref{sec:bus-control}) period
acknowledgment is negotiated. After Control, \bus returns to Idle or may
optionally send a response message.

\begin{figure}[h!]
  \centering
  \includegraphics[width=\linewidth]{timing/arb-crop}
  \caption{\textbf{\bus Arbitration.} \textmd{
    To begin a transaction, one or more nodes pull down on {\tt DOUT}.
    Here we show node~1 and node~3 requesting the bus at nearly the same time
    (node~1 shortly after node~3). Node~1 initially wins arbitration, but
    node~3 uses the priority arbitration cycle to claim the bus. The
    propagation delay of the data line between nodes is exaggerated to show
    the shoot-through nature of \bus. Momentary glitches caused by nodes
    transitioning from driving to forwarding are resolved before the next
    rising clock edge.
  }}
  \label{fig:arbitration}
\end{figure}

\subsection{Bus~Idle}
\label{sec:bus-idle}
In \bus Bus~Idle, all lines (clock and data) are high. All member nodes are in
forwarding state and the mediator node is waiting to begin arbitration.

\subsection{Arbitration}
\label{sec:bus-arbitration}
To begin arbitration, the bus must be in idle state.

To request to transmit on the bus, a node should pull its {\tt DOUT} line low.
All member nodes remain in forwarding state during arbitration, thus when
their {\tt DIN} line goes low, they are obligated to pull their {\tt DOUT}
line low. The mediator node, however, does {\bf NOT} pull its {\tt DOUT} line
low in response to its {\tt DIN} line going low. The mediator node only pulls
its {\tt DOUT} line low when it wishes to transmit on the bus. When the
mediator node's {\tt DIN} line goes low, it will pull the {\tt CLK} line low
and hold it low for some period $t_{long}$. During {\sc idle} (and thus
arbitration), member nodes must forward the clock signal.

By the end of the period $t_{long}$, the effect of the arbitration is
achieved. A member node is in one of three possible states:

\begin{quote}
\begin{enumerate}
  \item Clock low, {\tt DIN} high, {\tt DOUT} high -- Lost arbitration
    (didn't participate)
  \item Clock low, {\tt DIN} high, {\tt DOUT} low -- Won arbitration
  \item Clock low, {\tt DIN} low, {\tt DOUT} low -- Lost arbitration
    (either lost, or didn't participate)
\end{enumerate}
\end{quote}

\noindent
The rising edge of clock that follows $t_{long}$ commits the results of
arbitration and all participating member nodes advance their state machines
appropriately.

If the mediator node wishes to transmit on the bus, all member nodes will be in
the third state. Note this arbitration protocol introduces a {\em
topology-dependent priority}. Firstly, the mediator node has a greater priority
than any member node as its {\tt DOUT} will propagate around the entire data
loop. The priority of the member nodes is inversely related to their proximity
to the mediator node in the data loop. That is, the furthest node from the
mediator node, the node whose {\tt DIN} is connected to the mediator node's
{\tt DOUT}, has the highest priority of member nodes. The closest node to the
mediator node, the node whose {\tt DOUT} is connected to the mediator node's
{\tt DIN}, has the lowest priority.

At the end of $t_{long}$, the mediator node drives the clock high. The
normal arbitration phase ends on this rising edge. The next two clock edges
allow for a high-priority arbitration. As \bus priority is topology-dependent,
we provide a priority arbitration cycle to allow a low priority member node to
preempt transmissions. This priority mechanism is still topology-dependent,
that is, if Node~1 in \cref{fig:arbitration} had also attempted to send
a priority message, it would have won that arbitration as well. The priority
arbitration cycle is two clock edges (one clock cycle), the falling edge after
arbitration is for nodes to drive their priority requests onto the bus and the
rising edge is used to latch the results.  During priority arbitration, the
node that won the original arbitration {\bf must not} forward its {\tt DIN} to
{\tt DOUT}. At the end of priority
arbitration, if the original winner did not request a priority message, the
node must sample its {\tt DIN} line. If the line is still low there was no
priority message, if the {\tt DIN} line has gone high, however, the node
has lost priority arbitration and must back off to allow the priority message
requester to transmit.

Whichever node ultimately won arbitration transitions from a forwarding node
to a transmitting node. Nodes that lost arbitration revert to
Forwarding.{\sc Address\_Match}.

\begin{figure}
  \centering
  \begin{subfigure}[b]{.73\linewidth}
    \includegraphics[width=\linewidth]{timing/int-crop}
    \caption{Interjection timing with successful TX and ACK.}
    \label{fig:int-timing}
  \end{subfigure}
  %
  \begin{subfigure}[b]{.26\linewidth}
    \begin{enumerate}
      \footnotesize \sf
      \item After the transmitter sends all of its data it requests
        interjection by not forwarding \CLK.
      \item The mediator detects that a node has stopped forwarding \CLK.
      \item The mediator stops toggling \CLK and begins toggling \DAT\ -- the
        interjection sequence.
      \item After interjection, the mediator begins clocking again. Node~1
        discards the extra bits because they are not byte-aligned.
      \item The transmitter signals a complete message by driving Control
        Bit~0 high.
      \item The receiver ACK's the message by driving Control Bit~1 low.
      \item After control, the mediator stops forwarding \DAT, driving it
        high, and returning the bus to idle.
    \end{enumerate}
    \caption{Interjection Events.}
    \label{fig:int-details}
  \end{subfigure}
  %
  \caption{\textbf{\bus Interjection and Control.} \textmd{
      The \bus interjection sequence provides a reliable in-band reset signal.
      Any node may request that the mediator interject the bus by holding
      \CLKOUT high. The mediator detects this and generates an interjection by
      toggling \DAT while holding \CLK high. An interjection is always
      followed by a two-cycle control sequence that defines why the
      interjection occurred.
  }}
  \label{fig:int}
\end{figure}

\subsection{Message Transmission}
\label{sec:bus-transmission}
The falling edge after arbitration is defined as ``Begin~Transmission''. On this
edge, the transmitting node should switch its {\tt DOUT} mux from forwarding
{\tt DIN} to the transmit FIFO. Data is expected to be valid and stable during
every subsequent rising clock edge.

The first sequence of bits pushed onto \bus are the {\em address} bits. All
nodes on a \bus should listen until their address:
\begin{itemize}
  \item Matches: Node promotes itself from Forwarding.{\sc address\_match} to
    Receiving.{\sc receive}.
  \item Does Not Match: Node transitions from Forwarding.{\sc address\_match}
    to Forwarding.{\sc Ignore}.
\end{itemize}

There is no protocol-level delineation between address and data bits. The
transmitting node sends address$+$data as a continuous stream of bits (for
details on \bus addressing,
see~\ref{sec:spec-address}~\nameref{sec:spec-address}). Once a transmitter has
sent the complete transmission it interjects the bus.

Legal transmissions on \bus must be byte-aligned
(\ref{sec:spec-granularity}~\nameref{sec:spec-granularity}). The requirement
allows receiving nodes such as node~1 and node~3 in \cref{fig:int}
to disambiguate the significance of the last two bits received. A legal
transmission will end cleanly on a byte boundary if the node topologically
follows the transmitter (e.g.~node~3) or will end on a byte+2-bit boundary if
the node topologically precedes the transmitter (e.g.~node~1).

\subsection{Interjection}
\label{sec:bus-interjection}
During normal operation, interjection is only permitted after the first
32~bits of data have been transmitted
(\ref{sec:spec-interjection}~\nameref{sec:spec-interjection}). The
interjection mechanism, however, is also the \bus reset mechanism, and as such
member node interjection detectors {\bf must} always be active whenever a node
is not Idle.

A \bus interjection is defined as a series of pulses on the data line while the
clock line remains high. After $N$~pulses where $N \ge 3$, a node enters
interjection\footnote{
  While two pulses is sufficient to distinguish an interjection from normal
  data transmission, three pulses provides protection against spurious entry
  to interjection from a glitch on data lines.}.
Edges on the data line while the clock is low are ignored. This permits
potentially racy changes of {\tt DOUT} drivers to safely change on the falling
edge of the clock without potentially introducing spurious interjections.

The first rising clock edge after interjection is defined as ``Begin~Control''.
The next two clock edges define the control bits.

\subsubsection{Nesting Interjections}
In normal operation, interjections are not permitted to ``nest'', that is, the
bus may not be interjected while the control bits are being sent. If an
interjection sequence occurs during an existing interjection (which may only
occur if the bus is being ``rescued'' from some erroneous state), the new
interjection {\bf must} present control bits {\tt 00}.

\subsection{Control Bits}
\label{sec:bus-control}

\begin{figure}
  \includegraphics[width=\linewidth]{img/control_bits}
  \caption{\textbf{Control Bits.} \textmd{
      After an interjection, two control bits follow. The first bit is always
      set by the interjector and indicates whether the interjection was to
      signal the end of message (EoM). If the EoM bit is high, the receiving
      node is responsible for driving the second bit to acknowledge the
      message.  If the EoM bit is low, the interjector is responsible for
      driving the second bit. The TX/RX~Error (TRE) bit is set when a
      transmitting or receiving node encounters an error.
  }}
  \label{fig:control-bits}
\end{figure}

The two bits after an interjection are defined as Control~Bits.
\cref{fig:control-bits} is a flowchart indicating the semantic meaning
of the control bits and the resulting state. The first control bit is
unconditionally driven by the interjecting node. If a transmitting node has
interjected to indicate the end of transmission, it will put a {\tt 1} on the
bus for the first control bit. In all other cases the interjector must drive
{\tt 0} for the first control bit.

If the first control bit was {\tt 1} then the addressed receiver is
responsible for driving the second control bit. If the transmission was sent
to the broadcast address~(\ref{sec:control-broadcast}), all nodes---excluding
the transmitter which forwards---should drive the second control bit low to
acknowledge. The semantic provided to the transmitter of a broadcast message
then is either (1) no nodes received the message or (0) {\em at least} one
node received the message.

If instead the first control bit was {\tt 0} then the interjector is
responsible for driving the second control bit. If the interjector is the
transmitter or receiver {\bf and} the issue is related to the current
transmission (e.g. receiver buffer overflow) then the second bit should be set
high. If the purpose of the interjection is unrelated to the current
transmission (e.g. an external, high-priority, time-critical message) then the
second bit should be set low.

Unless the interjection carries a specific meaning as outlined in this
section, the {\sc 00: General Error} state should be used for general or
unclassified interjections as it carriers the least semantic meaning.

\subsection{Return to Idle}
\label{sec:bus-return-idle}
After latching the final Control~Bit (time~20 in \cref{fig:int}), one final
edge (time~22) is generated to formally enter {\sc idle}. If, however, the
data line is low at this edge, then it shall be considered the start of a new
arbitration cycle instead. The mediator node will pull the clock low again in
response and begin waiting for $t_{long}$.

By providing this edge, \bus enables member nodes with absolutely no sense of
time the ability to receive, react to, and respond to messages (albeit with
tight timing constraints).