drivers/gpu/drm/amd/display/dc/link/link_dpms.c: Disable FRL on dpms off

Author: mkopec

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

@@ -2453,6 +2453,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
 		}
 	}
 
+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+		dc_link_disable_frl(pipe_ctx->stream->link);
+
 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
 			!dp_is_128b_132b_signal(pipe_ctx)) {
 

drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.c

@@ -88,13 +88,13 @@ bool dc_link_perform_frl_training(struct dc_link *link,
 
 	/* Write source version = 1 */
 	write_buffer[0] = 0x01;
-	frl_write_scdc(link, HDMI_SCDC_SOURCE_VERSION, &write_buffer[0], 1);
+	frl_write_scdc(link, HDMI_SCDC_SOURCE_VERSION, write_buffer, 1);
 
 retrain:
 	/* Reset FRL rate */
 	write_buffer[0] = 0;
 	write_buffer[1] = 0;
-	frl_write_scdc(link, 0x30, &write_buffer[0], 2);
+	frl_write_scdc(link, HDMI_SCDC_CONFIG_0, write_buffer, 2);
 
 	/* ------------------------------------------------------------------ */
 	/* Step 2: Wait for FLT_READY                                          */
@@ -243,3 +243,13 @@ bool dc_link_perform_frl_training(struct dc_link *link,
 
 	return false;
 }
+
+void dc_link_disable_frl(struct dc_link *link)
+{
+	uint8_t write_buffer[2];
+
+	/* Inform the sink not to expect an FRL signal */
+	write_buffer[0] = 0;
+	write_buffer[1] = 0;
+	frl_write_scdc(link, HDMI_SCDC_CONFIG_0, write_buffer, 2);
+}

drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.h

@@ -34,4 +34,9 @@ struct link_resource;
 bool dc_link_perform_frl_training(struct dc_link *link,
 				  const struct link_resource *link_res);
 
+/*
+ * Disable FRL mode in the sink. Allows fallback to TMDS.
+ */
+void dc_link_disable_frl(struct dc_link *link);
+
 #endif /* __LINK_HDMI_FRL_TRAINING_H__ */