From 863dfd95d63b0ab8d3c0d05605aa77cad497dbc8 Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 09:57:13 -0500 Subject: [PATCH 01/16] nati_slsc_dts: Add device tree for SLSC Add device tree for SLSC to enable SPI based modules communication. Signed-off-by: George Huang Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 596 ++++++++++++++++++++++++++++++++++ 1 file changed, 596 insertions(+) create mode 100755 arch/arm/boot/dts/ni-slsc.dts diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts new file mode 100755 index 0000000000000..fae8a95e1d4b1 --- /dev/null +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -0,0 +1,596 @@ +/dts-v1/; +/include/ "ni-zynq.dtsi" + +/* NIDEVCODE 775E */ + +/ { + model = "NI SLSC"; + compatible = "ni,zynq", "xlnx,zynq-7000"; + + aliases { + spi1 = &spiController1; + /*spi2 = &spiController2;*/ /*confilct irq, disabled temproarily*/ + spi3 = &spiController3; + spi4 = &spiController4; + spi5 = &spiController5; + spi6 = &spiController6; + spi7 = &spiController7; + spi8 = &spiController8; + spi9 = &spiController9; + spi10 = &spiController10; + spi11 = &spiController11; + spi12 = &spiController12; + }; + + amba@0 { + + gpio: gpio@e000a000 { + /* You can specify GPIO settings here: + * + * gpioN-label String label. + * gpioN-direction "input" or "output". + * gpioN-settings "output" - specifies the GPIO state as "high" + * or "low". + * "input" - specifies GPIO interrupt settings as + * "none", "level-low", "level-high", + * "edge-falling", "edge-rising", or + * "edge-both". + */ + + /* GPIO1 (MIO1) */ + gpio1-label = "eth0_phy_interrupt"; + gpio1-direction = "input"; + gpio1-settings = "level-low"; + + /* GPIO15 (MIO15) */ + gpio15-label = "wdt_interrupt"; + gpio15-direction = "input"; + gpio15-settings = "edge-falling"; + + /* GPIO54 (EMIO0) */ + gpio54-label = "eth0_link_speed"; + gpio54-direction = "output"; + gpio54-settings = "low"; + + /* GPIO55 (EMIO1) */ + gpio55-label = "eth1_link_speed_1000"; + gpio55-direction = "output"; + gpio55-settings = "low"; + + /* GPIO56 (EMIO2) */ + gpio56-label = "eth1_link_speed_100"; + gpio56-direction = "output"; + gpio56-settings = "low"; + + /* GPIO57 (EMIO3) */ + gpio57-label = "eth1_phy_interrupt"; + gpio57-direction = "input"; + gpio57-settings = "level-low"; + }; + + i2c0: i2c@e0004000 { + nicpld@40 { + watchdogs { + boot-watchdog { + interrupt-parent = <&gpio>; + interrupts = <15 0>; + }; + }; + + leds { + status-0 { + label = "nilrt:status:yellow"; + max-brightness = <0xFFFF>; + }; + eth0-0 { + label = "nilrt:eth0:green"; + linux,default-trigger = + "e000b000.etherne:00:100Mb"; + }; + eth0-1 { + label = "nilrt:eth0:yellow"; + linux,default-trigger = + "e000b000.etherne:00:Gb"; + }; + }; + }; + + ds3231_rtc@68 { + status = "okay"; + }; + }; + + + spiController1: spi@0x80001000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80001000 0x1000>; + interrupts = <0 29 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot1"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible ="rohm,dh2228fv"; /*spidev cannot be used directly*/ + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + /*confilct irq @0x80002000, disabled temproarily*/ + /* + spiController2: spi@0x80002000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80002000 0x1000>; + interrupts = <0 30 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot2"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + */ + + spiController3: spi@0x80003000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80003000 0x1000>; + interrupts = <0 31 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot3"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController4: spi@0x80004000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80004000 0x1000>; + interrupts = <0 32 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot4"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController5: spi@0x80005000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80005000 0x1000>; + interrupts = <0 33 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot5"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController6: spi@0x80006000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80006000 0x1000>; + interrupts = <0 34 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot6"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController7: spi@0x80007000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80007000 0x1000>; + interrupts = <0 35 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot7"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController8: spi@0x80008000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80008000 0x1000>; + interrupts = <0 36 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot8"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController9: spi@0x80009000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80009000 0x1000>; + interrupts = <0 52 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot9"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController10: spi@0x8000A000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000A000 0x1000>; + interrupts = <0 53 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot10"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController11: spi@0x8000B000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000B000 0x1000>; + interrupts = <0 54 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot11"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController12: spi@0x8000C000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000C000 0x1000>; + interrupts = <0 55 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot12"; + reg = <0x0 0x1000000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + }; + + +}; + +&gem0 { + status = "okay"; + + /* No fpga_clk specified because we want our FPGA clock + * (fclk0) to always be 125 MHz. The bootloader sets + * fclk0 to 125 MHz and we just leave it like that. */ + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + cdns,emio-gpio-speed-1000 = <54>; + + phy0: phy@0 { + compatible = "micrel,KSZ9031"; + device_type = "ethernet-phy"; + reg = <0x0>; + /* Interrupt on GPIO1. */ + interrupts = <1 0>; + interrupt-parent = <&gpio>; + + /* Set RX_CLK Pad Skew [4:0] to 0b00000. */ + rxc-skew-ps = <0>; + }; +}; + +&gem1 { + status = "okay"; + + /* No fpga_clk specified because we want our FPGA clock (fclk0) to + * always be 125 MHz. The bootloader sets fclk0 to 125 MHz and we just + * leave it like that. */ + + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + cdns,emio-gpio-speed-1000 = <55>; + cdns,emio-gpio-speed-100 = <56>; + + phy1: phy@1 { + compatible = "micrel,KSZ9031"; + device_type = "ethernet-phy"; + reg = <0x1>; + /* Interrupt on GPIO57. */ + interrupts = <57 0>; + interrupt-parent = <&gpio>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&ni_uart0 { + status = "okay"; + transceiver = "RS-232"; +}; + +&ni_uart1 { + status = "okay"; + transceiver = "RS-232"; +}; + +&ni_uart2 { + status = "okay"; + transceiver = "RS-232"; +}; + +&ni_uart3 { + status = "okay"; + transceiver = "RS-232"; +}; + +&ni_uart4 { + status = "okay"; + transceiver = "RS-485"; +}; + +&ni_uart5 { + status = "okay"; + transceiver = "RS-485"; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&clkc { + /* Enable fclk0 for eth0 and eth1, fclk1 for serial. */ + fclk-enable = <0x3>; +}; From a73570b406a0f589fa7e567ad567d4c6de6890a4 Mon Sep 17 00:00:00 2001 From: George Huang Date: Thu, 3 Mar 2016 16:58:37 -0600 Subject: [PATCH 02/16] nati_slsc_dts: Correct SPI settings on device tree Adjust SPI interrupt assignemnt; fix MTD partition size, Fix spidev comaptible name string Signed-off-by: George Huang Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 73 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index fae8a95e1d4b1..f71a1a64e8487 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -9,7 +9,7 @@ aliases { spi1 = &spiController1; - /*spi2 = &spiController2;*/ /*confilct irq, disabled temproarily*/ + spi2 = &spiController2; spi3 = &spiController3; spi4 = &spiController4; spi5 = &spiController5; @@ -105,7 +105,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80001000 0x1000>; - interrupts = <0 29 4>; + interrupts = <0 31 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -121,7 +121,7 @@ partition@0 { label = "slsc_slot1"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; @@ -133,13 +133,12 @@ }; }; - /*confilct irq @0x80002000, disabled temproarily*/ - /* + spiController2: spi@0x80002000 { compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80002000 0x1000>; - interrupts = <0 30 4>; + interrupts = <0 32 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -154,7 +153,7 @@ partition@0 { label = "slsc_slot2"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; @@ -165,13 +164,13 @@ reg = <1>; }; }; - */ + spiController3: spi@0x80003000 { compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80003000 0x1000>; - interrupts = <0 31 4>; + interrupts = <0 33 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -186,7 +185,7 @@ partition@0 { label = "slsc_slot3"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; @@ -203,7 +202,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80004000 0x1000>; - interrupts = <0 32 4>; + interrupts = <0 34 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -218,13 +217,13 @@ partition@0 { label = "slsc_slot4"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -235,7 +234,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80005000 0x1000>; - interrupts = <0 33 4>; + interrupts = <0 35 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -250,13 +249,13 @@ partition@0 { label = "slsc_slot5"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -266,7 +265,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80006000 0x1000>; - interrupts = <0 34 4>; + interrupts = <0 36 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -281,13 +280,13 @@ partition@0 { label = "slsc_slot6"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -297,7 +296,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80007000 0x1000>; - interrupts = <0 35 4>; + interrupts = <0 37 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -312,13 +311,13 @@ partition@0 { label = "slsc_slot7"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -328,7 +327,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80008000 0x1000>; - interrupts = <0 36 4>; + interrupts = <0 38 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -343,13 +342,13 @@ partition@0 { label = "slsc_slot8"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -359,7 +358,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80009000 0x1000>; - interrupts = <0 52 4>; + interrupts = <0 54 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -374,13 +373,13 @@ partition@0 { label = "slsc_slot9"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -390,7 +389,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x8000A000 0x1000>; - interrupts = <0 53 4>; + interrupts = <0 55 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -405,13 +404,13 @@ partition@0 { label = "slsc_slot10"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -422,7 +421,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x8000B000 0x1000>; - interrupts = <0 54 4>; + interrupts = <0 56 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -437,13 +436,13 @@ partition@0 { label = "slsc_slot11"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -454,7 +453,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x8000C000 0x1000>; - interrupts = <0 55 4>; + interrupts = <0 57 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -469,13 +468,13 @@ partition@0 { label = "slsc_slot12"; - reg = <0x0 0x1000000>; + reg = <0x0 0x100000>; }; }; spidev@1 { - compatible = "spidev"; + compatible = "rohm,dh2228fv"; spi-max-frequency = <1000000>; reg = <1>; }; From d7f0f140e005954dbc1700da0b94edb61388bcb6 Mon Sep 17 00:00:00 2001 From: George Huang Date: Fri, 1 Apr 2016 11:18:35 -0500 Subject: [PATCH 03/16] nati_slsc_dts: fix IRQ for spi7/8 Correct the IRQ settings on the device tree for SPI controller 7 and 8 Signed-off-by: George Huang Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index f71a1a64e8487..6cb8fd3648a84 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -296,7 +296,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80007000 0x1000>; - interrupts = <0 37 4>; + interrupts = <0 52 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; @@ -327,7 +327,7 @@ compatible = "cdns,spi-r1p6"; status = "okay"; reg = <0x80008000 0x1000>; - interrupts = <0 38 4>; + interrupts = <0 53 4>; clock-names = "ref_clk", "pclk"; clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; From 3ac30b8deb65440ac2b6e4fa49f906ea23520766 Mon Sep 17 00:00:00 2001 From: siwu Date: Tue, 31 May 2016 14:57:35 -0500 Subject: [PATCH 04/16] nati_slsc_dts: Add SLSC FPGA to Device Tree Add SLSC FPGA to device tree to enable Usermode driver for module control and interrupt handling. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index 6cb8fd3648a84..b4ada2a7c72bc 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -99,7 +99,6 @@ status = "okay"; }; }; - spiController1: spi@0x80001000 { compatible = "cdns,spi-r1p6"; @@ -480,6 +479,12 @@ }; }; + slscfpga@80000000 { + compatible = "generic-uio"; + reg = <0x80000000 0x30000>; + interrupts = <0 29 0>; + }; + }; From c252f203dfbbd10460aec142ef5abb957a5e4579 Mon Sep 17 00:00:00 2001 From: Sien Date: Tue, 31 May 2016 17:44:28 -0500 Subject: [PATCH 05/16] nati_slsc_dts: Remove trailing whitespace Remove trailing whitespace on dts file since review-board will flag them as problem. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 52 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index b4ada2a7c72bc..a9ca61c72c2ae 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -19,7 +19,7 @@ spi9 = &spiController9; spi10 = &spiController10; spi11 = &spiController11; - spi12 = &spiController12; + spi12 = &spiController12; }; amba@0 { @@ -99,7 +99,7 @@ status = "okay"; }; }; - + spiController1: spi@0x80001000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -110,7 +110,7 @@ #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -124,14 +124,14 @@ }; }; - + spidev@1 { compatible ="rohm,dh2228fv"; /*spidev cannot be used directly*/ spi-max-frequency = <1000000>; reg = <1>; }; }; - + spiController2: spi@0x80002000 { compatible = "cdns,spi-r1p6"; @@ -142,7 +142,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -163,8 +163,8 @@ reg = <1>; }; }; - - + + spiController3: spi@0x80003000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -196,7 +196,7 @@ }; }; - + spiController4: spi@0x80004000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -228,7 +228,7 @@ }; }; - + spiController5: spi@0x80005000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -259,7 +259,7 @@ reg = <1>; }; }; - + spiController6: spi@0x80006000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -331,7 +331,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -344,7 +344,7 @@ reg = <0x0 0x100000>; }; }; - + spidev@1 { compatible = "rohm,dh2228fv"; @@ -352,7 +352,7 @@ reg = <1>; }; }; - + spiController9: spi@0x80009000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -362,7 +362,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -375,7 +375,7 @@ reg = <0x0 0x100000>; }; }; - + spidev@1 { compatible = "rohm,dh2228fv"; @@ -383,7 +383,7 @@ reg = <1>; }; }; - + spiController10: spi@0x8000A000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -393,7 +393,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -406,7 +406,7 @@ reg = <0x0 0x100000>; }; }; - + spidev@1 { compatible = "rohm,dh2228fv"; @@ -414,8 +414,8 @@ reg = <1>; }; }; - - + + spiController11: spi@0x8000B000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -425,7 +425,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -438,7 +438,7 @@ reg = <0x0 0x100000>; }; }; - + spidev@1 { compatible = "rohm,dh2228fv"; @@ -447,7 +447,7 @@ }; }; - + spiController12: spi@0x8000C000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -457,7 +457,7 @@ clocks = <&clkc 25>, <&clkc 34>; #address-cells = <1>; #size-cells = <0>; - + m25p80@0 { #address-cells = <1>; #size-cells = <1>; @@ -470,7 +470,7 @@ reg = <0x0 0x100000>; }; }; - + spidev@1 { compatible = "rohm,dh2228fv"; From abbb7fefb75984ff02b82d550dffb30cb8a53c44 Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 09:48:25 -0500 Subject: [PATCH 06/16] nati_slsc_dts: Correct device info in device tree Correct the device code and model name of SLSC in the device tree. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index a9ca61c72c2ae..0d307ea6e069f 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -1,10 +1,10 @@ /dts-v1/; /include/ "ni-zynq.dtsi" -/* NIDEVCODE 775E */ +/* NIDEVCODE 0x78AA */ / { - model = "NI SLSC"; + model = "NI SLSC-12001"; compatible = "ni,zynq", "xlnx,zynq-7000"; aliases { From 33d61aaecaa85ae17bc9e53b82b3d4a55d3d27e9 Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 11:10:18 -0500 Subject: [PATCH 07/16] nati_slsc_dts: pull in Tecate dts for 4.1 Linux kernel Pull in device tree settings of Tecate for Linux kernel 4.1 to improve compatibility of the SLSC hardware with the kernel. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 137 +++++++++++++++++----------------- 1 file changed, 69 insertions(+), 68 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index 0d307ea6e069f..a7d5ea7baac6e 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -73,7 +73,7 @@ watchdogs { boot-watchdog { interrupt-parent = <&gpio>; - interrupts = <15 0>; + interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>; }; }; @@ -491,110 +491,111 @@ }; &gem0 { - status = "okay"; - - /* No fpga_clk specified because we want our FPGA clock - * (fclk0) to always be 125 MHz. The bootloader sets - * fclk0 to 125 MHz and we just leave it like that. */ - - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - cdns,emio-gpio-speed-1000 = <54>; - - phy0: phy@0 { - compatible = "micrel,KSZ9031"; - device_type = "ethernet-phy"; - reg = <0x0>; - /* Interrupt on GPIO1. */ - interrupts = <1 0>; - interrupt-parent = <&gpio>; - - /* Set RX_CLK Pad Skew [4:0] to 0b00000. */ - rxc-skew-ps = <0>; - }; + status = "okay"; + + /* No fpga_clk specified because we want our FPGA clock + * (fclk0) to always be 125 MHz. The bootloader sets + * fclk0 to 125 MHz and we just leave it like that. */ + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + emio-speed-gpios = <0>, + <&gpio 54 0>; + + phy0: phy@0 { + compatible = "micrel,KSZ9031"; + device_type = "ethernet-phy"; + reg = <0x0>; + /* Interrupt on GPIO1. */ + interrupts = <1 8 /* IRQ_TYPE_LEVEL_LOW */>; + interrupt-parent = <&gpio>; + + /* Set RX_CLK Pad Skew [4:0] to 0b00000. */ + rxc-skew-ps = <0>; + }; }; &gem1 { - status = "okay"; - - /* No fpga_clk specified because we want our FPGA clock (fclk0) to - * always be 125 MHz. The bootloader sets fclk0 to 125 MHz and we just - * leave it like that. */ - - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - cdns,emio-gpio-speed-1000 = <55>; - cdns,emio-gpio-speed-100 = <56>; - - phy1: phy@1 { - compatible = "micrel,KSZ9031"; - device_type = "ethernet-phy"; - reg = <0x1>; - /* Interrupt on GPIO57. */ - interrupts = <57 0>; - interrupt-parent = <&gpio>; - }; + status = "okay"; + + /* No fpga_clk specified because we want our FPGA clock (fclk0) to + * always be 125 MHz. The bootloader sets fclk0 to 125 MHz and we just + * leave it like that. */ + + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + emio-speed-gpios = <&gpio 56 0>, + <&gpio 55 0>; + + phy1: phy@1 { + compatible = "micrel,KSZ9031"; + device_type = "ethernet-phy"; + reg = <0x1>; + /* Interrupt on GPIO57. */ + interrupts = <57 8 /* IRQ_TYPE_LEVEL_LOW */>; + interrupt-parent = <&gpio>; + }; }; &sdhci0 { - status = "okay"; + status = "okay"; }; &ni_uart0 { - status = "okay"; - transceiver = "RS-232"; + status = "okay"; + transceiver = "RS-232"; }; &ni_uart1 { - status = "okay"; - transceiver = "RS-232"; + status = "okay"; + transceiver = "RS-232"; }; &ni_uart2 { - status = "okay"; - transceiver = "RS-232"; + status = "okay"; + transceiver = "RS-232"; }; &ni_uart3 { - status = "okay"; - transceiver = "RS-232"; + status = "okay"; + transceiver = "RS-232"; }; &ni_uart4 { - status = "okay"; - transceiver = "RS-485"; + status = "okay"; + transceiver = "RS-485"; }; &ni_uart5 { - status = "okay"; - transceiver = "RS-485"; + status = "okay"; + transceiver = "RS-485"; }; &can0 { - status = "okay"; + status = "okay"; }; &can1 { - status = "okay"; + status = "okay"; }; &usb0 { - status = "okay"; - dr_mode = "peripheral"; + status = "okay"; + dr_mode = "peripheral"; }; &usb1 { - status = "okay"; - dr_mode = "host"; + status = "okay"; + dr_mode = "host"; }; &clkc { - /* Enable fclk0 for eth0 and eth1, fclk1 for serial. */ - fclk-enable = <0x3>; + /* Enable fclk0 for eth0 and eth1, fclk1 for serial. */ + fclk-enable = <0x3>; }; From f1fb662d3bb850df67a2601d4d68f411577f106e Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 13:52:27 -0500 Subject: [PATCH 08/16] nati_slsc_dts: Remove unused devices in dts Remove unused hardware from device tree to reflect the actual state of the SLSC hardware. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 63 ----------------------------------- 1 file changed, 63 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index a7d5ea7baac6e..f307498cc1f98 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -518,31 +518,6 @@ }; }; -&gem1 { - status = "okay"; - - /* No fpga_clk specified because we want our FPGA clock (fclk0) to - * always be 125 MHz. The bootloader sets fclk0 to 125 MHz and we just - * leave it like that. */ - - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - emio-speed-gpios = <&gpio 56 0>, - <&gpio 55 0>; - - phy1: phy@1 { - compatible = "micrel,KSZ9031"; - device_type = "ethernet-phy"; - reg = <0x1>; - /* Interrupt on GPIO57. */ - interrupts = <57 8 /* IRQ_TYPE_LEVEL_LOW */>; - interrupt-parent = <&gpio>; - }; -}; - &sdhci0 { status = "okay"; }; @@ -552,44 +527,6 @@ transceiver = "RS-232"; }; -&ni_uart1 { - status = "okay"; - transceiver = "RS-232"; -}; - -&ni_uart2 { - status = "okay"; - transceiver = "RS-232"; -}; - -&ni_uart3 { - status = "okay"; - transceiver = "RS-232"; -}; - -&ni_uart4 { - status = "okay"; - transceiver = "RS-485"; -}; - -&ni_uart5 { - status = "okay"; - transceiver = "RS-485"; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - &usb1 { status = "okay"; dr_mode = "host"; From a29348fc74fa36463ba50f874451844ccacd46bc Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 16:12:28 -0500 Subject: [PATCH 09/16] nati_slsc_dts: Use spidev as compatible type in dts Replace SLSC SPI controller compatible type with spidev rather than Rohm DAC to reflect what the SPI hardware to actually compatible with. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc.dts index f307498cc1f98..bcb878e0c3b26 100755 --- a/arch/arm/boot/dts/ni-slsc.dts +++ b/arch/arm/boot/dts/ni-slsc.dts @@ -126,7 +126,7 @@ spidev@1 { - compatible ="rohm,dh2228fv"; /*spidev cannot be used directly*/ + compatible ="spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -158,7 +158,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -190,7 +190,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -222,7 +222,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -254,7 +254,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -285,7 +285,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -316,7 +316,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -347,7 +347,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -378,7 +378,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -409,7 +409,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -441,7 +441,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; @@ -473,7 +473,7 @@ spidev@1 { - compatible = "rohm,dh2228fv"; + compatible = "spidev"; spi-max-frequency = <1000000>; reg = <1>; }; From ea42c24c77b9b4e2ecfdfe0730ea2d687df23746 Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 1 Jun 2016 16:21:17 -0500 Subject: [PATCH 10/16] nati_slsc_12001_dts: Rename dts file with model name Adding model number to the device tree to indicate that it is only valid for SLSC 12001 since a different dts file is required for a SLSC chassis that has different number of slots. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/{ni-slsc.dts => ni-slsc-12001.dts} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arm/boot/dts/{ni-slsc.dts => ni-slsc-12001.dts} (100%) diff --git a/arch/arm/boot/dts/ni-slsc.dts b/arch/arm/boot/dts/ni-slsc-12001.dts similarity index 100% rename from arch/arm/boot/dts/ni-slsc.dts rename to arch/arm/boot/dts/ni-slsc-12001.dts From 3408e42c2fb88166fee8429e38fb8f513e6c4f6a Mon Sep 17 00:00:00 2001 From: Sien Date: Thu, 2 Jun 2016 08:46:42 -0500 Subject: [PATCH 11/16] nati_slsc_12001_dts: Fix the format of the dts Removed "0x" prefix for the device code and replaced leading spaces by tabs so that the format is consistent with other dts files. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc-12001.dts | 1030 +++++++++++++-------------- 1 file changed, 515 insertions(+), 515 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/ni-slsc-12001.dts index bcb878e0c3b26..b7ef90521d9b3 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/ni-slsc-12001.dts @@ -1,538 +1,538 @@ /dts-v1/; /include/ "ni-zynq.dtsi" -/* NIDEVCODE 0x78AA */ +/* NIDEVCODE 78AA */ / { - model = "NI SLSC-12001"; - compatible = "ni,zynq", "xlnx,zynq-7000"; - - aliases { - spi1 = &spiController1; - spi2 = &spiController2; - spi3 = &spiController3; - spi4 = &spiController4; - spi5 = &spiController5; - spi6 = &spiController6; - spi7 = &spiController7; - spi8 = &spiController8; - spi9 = &spiController9; - spi10 = &spiController10; - spi11 = &spiController11; - spi12 = &spiController12; - }; - - amba@0 { - - gpio: gpio@e000a000 { - /* You can specify GPIO settings here: - * - * gpioN-label String label. - * gpioN-direction "input" or "output". - * gpioN-settings "output" - specifies the GPIO state as "high" - * or "low". - * "input" - specifies GPIO interrupt settings as - * "none", "level-low", "level-high", - * "edge-falling", "edge-rising", or - * "edge-both". - */ - - /* GPIO1 (MIO1) */ - gpio1-label = "eth0_phy_interrupt"; - gpio1-direction = "input"; - gpio1-settings = "level-low"; - - /* GPIO15 (MIO15) */ - gpio15-label = "wdt_interrupt"; - gpio15-direction = "input"; - gpio15-settings = "edge-falling"; - - /* GPIO54 (EMIO0) */ - gpio54-label = "eth0_link_speed"; - gpio54-direction = "output"; - gpio54-settings = "low"; - - /* GPIO55 (EMIO1) */ - gpio55-label = "eth1_link_speed_1000"; - gpio55-direction = "output"; - gpio55-settings = "low"; - - /* GPIO56 (EMIO2) */ - gpio56-label = "eth1_link_speed_100"; - gpio56-direction = "output"; - gpio56-settings = "low"; - - /* GPIO57 (EMIO3) */ - gpio57-label = "eth1_phy_interrupt"; - gpio57-direction = "input"; - gpio57-settings = "level-low"; - }; - - i2c0: i2c@e0004000 { - nicpld@40 { - watchdogs { - boot-watchdog { - interrupt-parent = <&gpio>; - interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>; - }; - }; - - leds { - status-0 { - label = "nilrt:status:yellow"; - max-brightness = <0xFFFF>; - }; - eth0-0 { - label = "nilrt:eth0:green"; - linux,default-trigger = - "e000b000.etherne:00:100Mb"; - }; - eth0-1 { - label = "nilrt:eth0:yellow"; - linux,default-trigger = - "e000b000.etherne:00:Gb"; - }; - }; - }; - - ds3231_rtc@68 { - status = "okay"; - }; - }; - - spiController1: spi@0x80001000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80001000 0x1000>; - interrupts = <0 31 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot1"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible ="spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController2: spi@0x80002000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80002000 0x1000>; - interrupts = <0 32 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot2"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController3: spi@0x80003000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80003000 0x1000>; - interrupts = <0 33 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot3"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController4: spi@0x80004000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80004000 0x1000>; - interrupts = <0 34 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot4"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController5: spi@0x80005000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80005000 0x1000>; - interrupts = <0 35 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot5"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - spiController6: spi@0x80006000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80006000 0x1000>; - interrupts = <0 36 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot6"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - spiController7: spi@0x80007000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80007000 0x1000>; - interrupts = <0 52 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot7"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - spiController8: spi@0x80008000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80008000 0x1000>; - interrupts = <0 53 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot8"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - spiController9: spi@0x80009000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x80009000 0x1000>; - interrupts = <0 54 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot9"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - spiController10: spi@0x8000A000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x8000A000 0x1000>; - interrupts = <0 55 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot10"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController11: spi@0x8000B000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x8000B000 0x1000>; - interrupts = <0 56 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot11"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - - spiController12: spi@0x8000C000 { - compatible = "cdns,spi-r1p6"; - status = "okay"; - reg = <0x8000C000 0x1000>; - interrupts = <0 57 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 25>, <&clkc 34>; - #address-cells = <1>; - #size-cells = <0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80","jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <5000000>; - - partition@0 { - label = "slsc_slot12"; - reg = <0x0 0x100000>; - }; - }; - - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <1000000>; - reg = <1>; - }; - }; - - slscfpga@80000000 { - compatible = "generic-uio"; - reg = <0x80000000 0x30000>; - interrupts = <0 29 0>; - }; - - }; + model = "NI SLSC-12001"; + compatible = "ni,zynq", "xlnx,zynq-7000"; + + aliases { + spi1 = &spiController1; + spi2 = &spiController2; + spi3 = &spiController3; + spi4 = &spiController4; + spi5 = &spiController5; + spi6 = &spiController6; + spi7 = &spiController7; + spi8 = &spiController8; + spi9 = &spiController9; + spi10 = &spiController10; + spi11 = &spiController11; + spi12 = &spiController12; + }; + + amba@0 { + + gpio: gpio@e000a000 { + /* You can specify GPIO settings here: + * + * gpioN-label String label. + * gpioN-direction "input" or "output". + * gpioN-settings "output" - specifies the GPIO state as "high" + * or "low". + * "input" - specifies GPIO interrupt settings as + * "none", "level-low", "level-high", + * "edge-falling", "edge-rising", or + * "edge-both". + */ + + /* GPIO1 (MIO1) */ + gpio1-label = "eth0_phy_interrupt"; + gpio1-direction = "input"; + gpio1-settings = "level-low"; + + /* GPIO15 (MIO15) */ + gpio15-label = "wdt_interrupt"; + gpio15-direction = "input"; + gpio15-settings = "edge-falling"; + + /* GPIO54 (EMIO0) */ + gpio54-label = "eth0_link_speed"; + gpio54-direction = "output"; + gpio54-settings = "low"; + + /* GPIO55 (EMIO1) */ + gpio55-label = "eth1_link_speed_1000"; + gpio55-direction = "output"; + gpio55-settings = "low"; + + /* GPIO56 (EMIO2) */ + gpio56-label = "eth1_link_speed_100"; + gpio56-direction = "output"; + gpio56-settings = "low"; + + /* GPIO57 (EMIO3) */ + gpio57-label = "eth1_phy_interrupt"; + gpio57-direction = "input"; + gpio57-settings = "level-low"; + }; + + i2c0: i2c@e0004000 { + nicpld@40 { + watchdogs { + boot-watchdog { + interrupt-parent = <&gpio>; + interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>; + }; + }; + + leds { + status-0 { + label = "nilrt:status:yellow"; + max-brightness = <0xFFFF>; + }; + eth0-0 { + label = "nilrt:eth0:green"; + linux,default-trigger = + "e000b000.etherne:00:100Mb"; + }; + eth0-1 { + label = "nilrt:eth0:yellow"; + linux,default-trigger = + "e000b000.etherne:00:Gb"; + }; + }; + }; + + ds3231_rtc@68 { + status = "okay"; + }; + }; + + spiController1: spi@0x80001000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80001000 0x1000>; + interrupts = <0 31 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot1"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible ="spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController2: spi@0x80002000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80002000 0x1000>; + interrupts = <0 32 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot2"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController3: spi@0x80003000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80003000 0x1000>; + interrupts = <0 33 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot3"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController4: spi@0x80004000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80004000 0x1000>; + interrupts = <0 34 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot4"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController5: spi@0x80005000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80005000 0x1000>; + interrupts = <0 35 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot5"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController6: spi@0x80006000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80006000 0x1000>; + interrupts = <0 36 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot6"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController7: spi@0x80007000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80007000 0x1000>; + interrupts = <0 52 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot7"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController8: spi@0x80008000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80008000 0x1000>; + interrupts = <0 53 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot8"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController9: spi@0x80009000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x80009000 0x1000>; + interrupts = <0 54 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot9"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + spiController10: spi@0x8000A000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000A000 0x1000>; + interrupts = <0 55 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot10"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController11: spi@0x8000B000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000B000 0x1000>; + interrupts = <0 56 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot11"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + + spiController12: spi@0x8000C000 { + compatible = "cdns,spi-r1p6"; + status = "okay"; + reg = <0x8000C000 0x1000>; + interrupts = <0 57 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 25>, <&clkc 34>; + #address-cells = <1>; + #size-cells = <0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80","jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <5000000>; + + partition@0 { + label = "slsc_slot12"; + reg = <0x0 0x100000>; + }; + }; + + + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + reg = <1>; + }; + }; + + slscfpga@80000000 { + compatible = "generic-uio"; + reg = <0x80000000 0x30000>; + interrupts = <0 29 0>; + }; + + }; }; &gem0 { - status = "okay"; - - /* No fpga_clk specified because we want our FPGA clock - * (fclk0) to always be 125 MHz. The bootloader sets - * fclk0 to 125 MHz and we just leave it like that. */ - - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - emio-speed-gpios = <0>, - <&gpio 54 0>; - - phy0: phy@0 { - compatible = "micrel,KSZ9031"; - device_type = "ethernet-phy"; - reg = <0x0>; - /* Interrupt on GPIO1. */ - interrupts = <1 8 /* IRQ_TYPE_LEVEL_LOW */>; - interrupt-parent = <&gpio>; - - /* Set RX_CLK Pad Skew [4:0] to 0b00000. */ - rxc-skew-ps = <0>; - }; + status = "okay"; + + /* No fpga_clk specified because we want our FPGA clock + * (fclk0) to always be 125 MHz. The bootloader sets + * fclk0 to 125 MHz and we just leave it like that. */ + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + emio-speed-gpios = <0>, + <&gpio 54 0>; + + phy0: phy@0 { + compatible = "micrel,KSZ9031"; + device_type = "ethernet-phy"; + reg = <0x0>; + /* Interrupt on GPIO1. */ + interrupts = <1 8 /* IRQ_TYPE_LEVEL_LOW */>; + interrupt-parent = <&gpio>; + + /* Set RX_CLK Pad Skew [4:0] to 0b00000. */ + rxc-skew-ps = <0>; + }; }; &sdhci0 { - status = "okay"; + status = "okay"; }; &ni_uart0 { - status = "okay"; - transceiver = "RS-232"; + status = "okay"; + transceiver = "RS-232"; }; &usb1 { - status = "okay"; - dr_mode = "host"; + status = "okay"; + dr_mode = "host"; }; &clkc { - /* Enable fclk0 for eth0 and eth1, fclk1 for serial. */ - fclk-enable = <0x3>; + /* Enable fclk0 for eth0 and eth1, fclk1 for serial. */ + fclk-enable = <0x3>; }; From 7696312488cec1dbe43af588504556f2ec64c7b0 Mon Sep 17 00:00:00 2001 From: Sien Date: Thu, 2 Jun 2016 14:24:11 -0500 Subject: [PATCH 12/16] nati_slsc_12001_dts: set SLSC FPGA compatible id to ni,slscfpga Rename the compatible id of slscfpga from generic-uio to ni,slscfpga so that it can better describe the hardware. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc-12001.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/ni-slsc-12001.dts index b7ef90521d9b3..bc8f117915ff8 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/ni-slsc-12001.dts @@ -480,7 +480,7 @@ }; slscfpga@80000000 { - compatible = "generic-uio"; + compatible = "ni,slscfpga"; reg = <0x80000000 0x30000>; interrupts = <0 29 0>; }; From 1c332df1f7f61fd19cb7f960ad7a6daf6799a82f Mon Sep 17 00:00:00 2001 From: Sien Date: Fri, 17 Jun 2016 16:34:04 -0500 Subject: [PATCH 13/16] nati_slsc_12001_dts: Add AD7291 ADC to device tree Add AD7291 ADC to device tree for monitoring chassis temperature, fan, and battery. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc-12001.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/ni-slsc-12001.dts index bc8f117915ff8..d2eb2dab4bf0c 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/ni-slsc-12001.dts @@ -100,6 +100,16 @@ }; }; + i2c1: i2c@e0005000 { + status = "okay"; + + ad7291_adc@2c { + compatible = "ad7291"; + status = "okay"; + reg = <0x2C>; + }; + } ; + spiController1: spi@0x80001000 { compatible = "cdns,spi-r1p6"; status = "okay"; From bc30972515b2f77374d696ceafdb7502d5cd435d Mon Sep 17 00:00:00 2001 From: Sien Date: Wed, 29 Jun 2016 09:25:00 -0500 Subject: [PATCH 14/16] nati_slsc_12001_dts: Enforce level trigger for slscfpga IRQ Resolve a discrepancy of interrupt type between the slscfpga in dts and the actual fpga hardware by updating slscfpga device in dts to be level high trigger instead of default since the default is edge trigger but the FPGA implementation is level trigger. Signed-off-by: Sien Wu Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc-12001.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/ni-slsc-12001.dts index d2eb2dab4bf0c..cd5ccc0403092 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/ni-slsc-12001.dts @@ -492,7 +492,7 @@ slscfpga@80000000 { compatible = "ni,slscfpga"; reg = <0x80000000 0x30000>; - interrupts = <0 29 0>; + interrupts = <0 29 4>; }; }; From 4ff558bb2e7e22dc30080d9521251ce44f1736e6 Mon Sep 17 00:00:00 2001 From: Sien Wu Date: Wed, 24 Aug 2016 10:49:53 -0500 Subject: [PATCH 15/16] nati_slsc_12001_dts: Reduce SPI max frequency m25p80 device Limit the max SPI frequency for m25p80 to 1MHz. Allowing faster SPI clock for the m25p80 on SLSC module would result in potential failure when talking to a module that only meets the 1MHz minimum SPI clock timing. Signed-off-by: Sien Wu Acked-by: Brad Keryan Natinst-ReviewBoard-ID 150232 Signed-off-by: Kae Woei Kang --- arch/arm/boot/dts/ni-slsc-12001.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/ni-slsc-12001.dts index cd5ccc0403092..745b99241f552 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/ni-slsc-12001.dts @@ -126,7 +126,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot1"; @@ -158,7 +158,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot2"; @@ -190,7 +190,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot3"; @@ -222,7 +222,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot4"; @@ -254,7 +254,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot5"; @@ -285,7 +285,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot6"; @@ -316,7 +316,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot7"; @@ -347,7 +347,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot8"; @@ -378,7 +378,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot9"; @@ -409,7 +409,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot10"; @@ -441,7 +441,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot11"; @@ -473,7 +473,7 @@ #size-cells = <1>; compatible = "m25p80","jedec,spi-nor"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; partition@0 { label = "slsc_slot12"; From c3b90c1d35aff7cbf598c8d85a9cbaecfccb046d Mon Sep 17 00:00:00 2001 From: Kae Woei Kang Date: Mon, 21 Apr 2025 12:55:19 +0800 Subject: [PATCH 16/16] ARM: ni-slsc-12001.dts: Update i2c bindings zynq-700.dtsi contains i2c0 and i2c1 device tree node phandles. Referencing i2c0 and i2c1 phandle for overriding i2c bindings. Signed-off-by: Kae Woei Kang --- .../boot/dts/{ => xilinx}/ni-slsc-12001.dts | 90 ++++++++++--------- 1 file changed, 48 insertions(+), 42 deletions(-) rename arch/arm/boot/dts/{ => xilinx}/ni-slsc-12001.dts (93%) diff --git a/arch/arm/boot/dts/ni-slsc-12001.dts b/arch/arm/boot/dts/xilinx/ni-slsc-12001.dts similarity index 93% rename from arch/arm/boot/dts/ni-slsc-12001.dts rename to arch/arm/boot/dts/xilinx/ni-slsc-12001.dts index 745b99241f552..92556f50ffd70 100755 --- a/arch/arm/boot/dts/ni-slsc-12001.dts +++ b/arch/arm/boot/dts/xilinx/ni-slsc-12001.dts @@ -68,48 +68,6 @@ gpio57-settings = "level-low"; }; - i2c0: i2c@e0004000 { - nicpld@40 { - watchdogs { - boot-watchdog { - interrupt-parent = <&gpio>; - interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>; - }; - }; - - leds { - status-0 { - label = "nilrt:status:yellow"; - max-brightness = <0xFFFF>; - }; - eth0-0 { - label = "nilrt:eth0:green"; - linux,default-trigger = - "e000b000.etherne:00:100Mb"; - }; - eth0-1 { - label = "nilrt:eth0:yellow"; - linux,default-trigger = - "e000b000.etherne:00:Gb"; - }; - }; - }; - - ds3231_rtc@68 { - status = "okay"; - }; - }; - - i2c1: i2c@e0005000 { - status = "okay"; - - ad7291_adc@2c { - compatible = "ad7291"; - status = "okay"; - reg = <0x2C>; - }; - } ; - spiController1: spi@0x80001000 { compatible = "cdns,spi-r1p6"; status = "okay"; @@ -500,6 +458,10 @@ }; +&watchdog0 { + reset-on-timeout; +}; + &gem0 { status = "okay"; @@ -528,6 +490,50 @@ }; }; +&i2c0 { + /* Override ni-zynq.dtsi */ + nicpld@40 { + watchdogs { + boot-watchdog { + interrupt-parent = <&gpio>; + interrupts = <15 2 /* IRQ_TYPE_EDGE_FALLING */>; + }; + }; + + leds { + status-0 { + label = "nilrt:status:yellow"; + max-brightness = <0xFFFF>; + }; + eth0-0 { + label = "nilrt:eth0:green"; + linux,default-trigger = + "e000b000.etherne:00:100Mb"; + }; + eth0-1 { + label = "nilrt:eth0:yellow"; + linux,default-trigger = + "e000b000.etherne:00:Gb"; + }; + }; + }; + + ds3231_rtc@68 { + status = "okay"; + }; +}; + +&i2c1 { + /* Override ni-zynq.dtsi */ + status = "okay"; + + ad7291_adc@2c { + compatible = "ad7291"; + status = "okay"; + reg = <0x2C>; + }; +}; + &sdhci0 { status = "okay"; };