de0_nano: Integrate de0 nano to new format

Author: stffrdhrn

de0_nano/Makefile

@@ -1,16 +1,28 @@
 ---
 title: De0 Nano
 layout: page
-parent: Platforms
+parent: FuseSoC
 ---
 
-## DE0 Nano Tutorial
+## Prerequisites
 
-If you downloaded the tutorials as a release archive, you can directly
-start. If you have cloned the git repository, you instead need to
-follow the instructions for building the hardware and software as
-described below. Please also follow the
-[common tutorial setup](../index.html).
+#### System
+
+ * An x86 Linux workstation
+ * The `curl` command line utilities
+ * OpenOCD
+ * The quartus FPGA design software
+ * `fusesoc` - The [FuseSoC build system](../fusesoc.html).
+ * `or1k-elf-` Toolchain as installed in our [newlib tutorial](../newlib.html).
+
+#### Files
+
+ * [hello.c](../sw/hello/hello.c) - A Hello World test program.
+ * [timer.c](../sw/timer/timer.c) - A baremetal example using the OpenRISC timer api's provided by newlib.
+
+## DE0 Nano
+
+To confirm you have all of the required tools installed check with the following:
 
 To run the demo you need:
 
@@ -36,12 +48,35 @@ the bottom of the board as depicted below.
 
 ![uart](doc/uart.png "Connect UART to board")
 
+### Setup the Environment
+
+To get started we will want to have a directory with all
+of our build files in one place.
+
+```bash
+mkdir /tmp/or1k-de0nano
+cd /tmp/or1k-de0nano
+
+curl -L -O https://openrisc.io/tutorials/sw/hello/hello.c
+curl -L -O https://openrisc.io/tutorials/sw/timer/timer.c
+
+fusesoc library add de0_nano https://github.com/olofk/de0_nano.git
+```
+
+### Build the FPGA bitstream
+
+```bash
+fusesoc build de0_nano
+```
+
 ### Program the FPGA bitstream
 
 Once the board is setup, you can download the FPGA bitstream by
 running
 
-	make program
+```bash
+fusesoc pgm de0_nano
+```
 
 ### Start the OpenOCD daemon
 
@@ -69,11 +104,18 @@ You should see the LEDs counting and UART output once a second.
 
 You can rebuilt the hardware by running:
 
-	make build-hw
+```bash
+fusesoc build de0_nano
+```
 
 ## (Re-)build the software
 
 Some example software is available, that you can (re-)build for the
 DE0 nano board by running
 
-	make build-sw
+```bash
+CFLAGS=-mboard=de0_nano -DDE0_NANO
+
+or1k-elf-gcc -g -o hello.elf ${CFLAGS} ../sw/hello/hello.c
+or1k-elf-gcc -g -o timer.elf ${CFLAGS} ../sw/timer/timer.c
+```

de0_nano/index.md

@@ -0,0 +1,39 @@
+---
+title: FuseSoC
+layout: page
+nav_order: 3
+parent: Platforms
+---
+
+The FuseSoC build system, dependency manager and fpga integration platform
+allows for easy creation of OpenRISC systems.  If is featured in our
+[Quick Start with Docker Images](images/) as our main fpga development
+platform.  For in depth documentation see:
+
+ * [FuseSoC Manual](https://fusesoc.readthedocs.io/en/stable/index.html) - Full documentation.
+ * [olofk/fusesoc](https://github.com/olofk/fusesoc) - The github project
+
+## Installing FuseSoC
+
+FuseSoC is a python program and can be installed using `pip`.  The easiest way to get started is
+simplly:
+
+```
+pip3 install --upgrade --user fusesoc
+```
+
+## Available SoCs
+
+In our tutorials we will mainly use the `mor1kx-generic` fusesoc
+SoC but there are a few more out there.  Also available are:
+
+  * [stffrdhrn/mor1kx-generic](https://github.com/stffrdhrn/mor1kx-generic) - A generic SoC that can be used as a starting point.
+    It supports both [mor1kx](https://github.com/openrisc/mor1kx) and [marocchino](https://github.com/openrisc/or1k_marocchino) CPU cores
+    with both [iverilog](https://bleyer.org/icarus/) and [verilator](https://www.veripool.org/verilator/) simulation backends.
+  * [olofk/de0_nano](https://github.com/olofk/de0_nano) - An SoC for the [Terasic De0 Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593) FPGA development board.
+  * [stffrdhrn/de0_nano-multicore](https://github.com/stffrdhrn/de0_nano-multicore) - A De0 Nano SoC supporting multiple mor1kx cores used to test SMP Linux.
+  * [orpsoc-cores](https://github.com/openrisc/orpsoc-cores/tree/master/systems) - There are also several SoC's that have not yet been converted from the orpsoc-cores to fusesoc stand alone cores structure.  These include support for de1, de2 and atlys FPGA boards.
+
+If you have developed fusesoc support for a board not mentioned here please mail the [OpenRISC mailing](mailto:linux-openrisc@vger.kernel.org)
+list or create a PR for this tutorial and we can add it here.
+

fusesoc.md

@@ -26,7 +26,7 @@ This downloads all free and open tools. Unfortunately, you will still
 need to install closed (but free) tools from the FPGA vendors:
 
 * [Altera Quartus Prime](#altera-quartus-prime) for Altera FPGAs
-  ([DE0 nano](de0_nano/README.md).
+  ([DE0 nano](de0_nano/)).
 
 You can now start with the [tutorials](#tutorials).