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ThomasLeykimphil
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UART DEM: Port to new Debug Packet format
In addition to porting to the new header format, this commit - adds cocotb-based tests for most functionality, and - imports fixes done in OpTiMSoC when testing Linux (see optimsoc/optimsoc#78).
1 parent 041d003 commit 4117c85

9 files changed

Lines changed: 1311 additions & 115 deletions

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modules/dem_uart/common/osd_dem_uart.sv

Lines changed: 92 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -19,125 +19,160 @@ import dii_package::dii_flit;
1919
module osd_dem_uart
2020
(input clk, rst,
2121

22-
input dii_flit debug_in, output debug_in_ready,
23-
output dii_flit debug_out, input debug_out_ready,
22+
input dii_flit debug_in, output debug_in_ready,
23+
output dii_flit debug_out, input debug_out_ready,
2424

25-
input [15:0] id,
25+
input [15:0] id,
2626

27-
output drop,
27+
output drop,
2828

29-
input [7:0] out_char,
30-
input out_valid,
31-
output reg out_ready,
29+
input [7:0] out_char,
30+
input out_valid,
31+
output reg out_ready,
3232

3333
output reg [7:0] in_char,
34-
output reg in_valid,
35-
input in_ready);
36-
37-
logic reg_request;
38-
logic reg_write;
39-
logic [15:0] reg_addr;
40-
logic [1:0] reg_size;
41-
logic [15:0] reg_wdata;
42-
logic reg_ack;
43-
logic reg_err;
44-
logic [15:0] reg_rdata;
45-
46-
assign reg_ack = 0;
47-
assign reg_err = 0;
48-
assign reg_rdata = 0;
49-
50-
logic stall;
34+
output reg in_valid,
35+
input in_ready
36+
);
37+
38+
localparam TYPE_EVENT = 2'b10;
39+
localparam TYPE_SUB_EVENT_LAST = 4'b0000;
40+
41+
logic stall;
5142
assign drop = stall;
5243

53-
dii_flit c_uart_out, c_uart_in;
44+
dii_flit c_uart_out, c_uart_in;
5445
logic c_uart_out_ready, c_uart_in_ready;
5546

47+
reg [15:0] event_dest;
48+
reg [7:0] out_char_buf;
49+
5650
osd_regaccess_layer
57-
#(.MODID(16'h2), .MODVERSION(16'h0),
51+
#(.MOD_VENDOR(16'h1), .MOD_TYPE(16'h5), .MOD_VERSION(16'h0),
5852
.MAX_REG_SIZE(16), .CAN_STALL(1))
59-
u_regaccess(.*,
53+
u_regaccess(.clk (clk), .rst (rst), .id (id),
54+
.debug_in (debug_in),
55+
.debug_in_ready (debug_in_ready),
56+
.debug_out (debug_out),
57+
.debug_out_ready (debug_out_ready),
6058
.module_in (c_uart_out),
6159
.module_in_ready (c_uart_out_ready),
6260
.module_out (c_uart_in),
63-
.module_out_ready (c_uart_in_ready));
61+
.module_out_ready (c_uart_in_ready),
62+
.stall (stall),
63+
.event_dest(event_dest),
64+
.reg_request (),
65+
.reg_write (),
66+
.reg_addr (),
67+
.reg_size (),
68+
.reg_wdata (),
69+
.reg_ack (1'b0),
70+
.reg_err (1'b0),
71+
.reg_rdata (16'h0));
72+
73+
enum { STATE_IDLE, STATE_HDR_DEST, STATE_HDR_SRC, STATE_HDR_FLAGS,
74+
STATE_XFER } state_tx, state_rx;
6475

65-
enum { STATE_IDLE, STATE_HEADER, STATE_XFER } stateTx, stateRx;
6676
always @(posedge clk) begin
6777
if (rst) begin
68-
stateTx <= STATE_IDLE;
69-
stateRx <= STATE_IDLE;
78+
state_tx <= STATE_IDLE;
79+
state_rx <= STATE_IDLE;
7080
end else begin
71-
case (stateTx)
81+
case (state_tx)
7282
STATE_IDLE: begin
73-
if (out_valid & !stall & c_uart_out_ready) begin
74-
stateTx <= STATE_HEADER;
83+
if (out_valid & !stall) begin
84+
state_tx <= STATE_HDR_DEST;
85+
out_char_buf <= out_char;
86+
end
87+
end
88+
STATE_HDR_DEST: begin
89+
if (c_uart_out_ready) begin
90+
state_tx <= STATE_HDR_SRC;
7591
end
7692
end
77-
STATE_HEADER: begin
93+
STATE_HDR_SRC: begin
7894
if (c_uart_out_ready) begin
79-
stateTx <= STATE_XFER;
95+
state_tx <= STATE_HDR_FLAGS;
96+
end
97+
end
98+
STATE_HDR_FLAGS: begin
99+
if (c_uart_out_ready) begin
100+
state_tx <= STATE_XFER;
80101
end
81102
end
82103
STATE_XFER: begin
83104
if (c_uart_out_ready) begin
84-
stateTx <= STATE_IDLE;
105+
state_tx <= STATE_IDLE;
85106
end
86107
end
87-
endcase // case (stateTx)
108+
endcase
88109

89-
case (stateRx)
110+
case (state_rx)
90111
STATE_IDLE: begin
91112
if (c_uart_in.valid) begin
92-
stateRx <= STATE_HEADER;
113+
state_rx <= STATE_HDR_SRC;
93114
end
94115
end
95-
STATE_HEADER: begin
116+
STATE_HDR_SRC: begin
96117
if (c_uart_in.valid) begin
97-
stateRx <= STATE_XFER;
118+
state_rx <= STATE_HDR_FLAGS;
119+
end
120+
end
121+
STATE_HDR_FLAGS: begin
122+
if (c_uart_in.valid) begin
123+
state_rx <= STATE_XFER;
98124
end
99125
end
100126
STATE_XFER: begin
101127
if (c_uart_in.valid & in_ready) begin
102-
stateRx <= STATE_IDLE;
128+
state_rx <= STATE_IDLE;
103129
end
104130
end
105-
endcase // case (stateRx)
131+
endcase
106132
end // else: !if(rst)
107133
end
108134

109-
always @(*) begin
135+
always_comb begin
110136
c_uart_out.valid = 0;
111137
c_uart_out.last = 0;
112-
c_uart_out.data = 'x;
138+
c_uart_out.data = 16'h0;
113139
out_ready = 0;
114140

115-
case (stateTx)
141+
case (state_tx)
116142
STATE_IDLE: begin
117-
c_uart_out.valid = out_valid & !stall;
118-
c_uart_out.data = 0;
143+
out_ready = !stall;
119144
end
120-
STATE_HEADER: begin
145+
STATE_HDR_DEST: begin
121146
c_uart_out.valid = 1;
122-
c_uart_out.data = {2'b01, 4'h01, 10'(id)};
147+
c_uart_out.data = 0; // event_dest
148+
end
149+
STATE_HDR_SRC: begin
150+
c_uart_out.valid = 1;
151+
c_uart_out.data = id;
152+
end
153+
STATE_HDR_FLAGS: begin
154+
c_uart_out.valid = 1;
155+
c_uart_out.data = {TYPE_EVENT, TYPE_SUB_EVENT_LAST, 10'h0};
123156
end
124157
STATE_XFER: begin
125158
c_uart_out.valid = 1;
126-
c_uart_out.data = {8'h0, out_char};
159+
c_uart_out.data = {8'h0, out_char_buf};
127160
c_uart_out.last = 1;
128-
out_ready = c_uart_out_ready;
129161
end
130-
endcase // case (stateTx)
162+
endcase
131163

132164
c_uart_in_ready = 0;
133165
in_valid = 0;
134-
in_char = 'x;
166+
in_char = 8'h0;
135167

136-
case (stateRx)
168+
case (state_rx)
137169
STATE_IDLE: begin
138170
c_uart_in_ready = 1;
139171
end
140-
STATE_HEADER: begin
172+
STATE_HDR_SRC: begin
173+
c_uart_in_ready = 1;
174+
end
175+
STATE_HDR_FLAGS: begin
141176
c_uart_in_ready = 1;
142177
end
143178
STATE_XFER: begin

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