deps: Update to Amaranth 0.5.4 and LUNA 0.2.0.

Author: zyp

orbtrace/amaranth_glue/luna.py

@@ -38,21 +38,21 @@ def __init__(self, pads, wrapper, *args, **kwargs):
             [
                 ('data', [('i', 8, DIR_FANIN), ('o', 8, DIR_FANOUT), ('oe', 1, DIR_FANOUT)]),
                 ('clk', [('i', 1, DIR_FANIN)] if hasattr(pads, 'clk') else [('o', 1, DIR_FANOUT)]),
-                ('stp', 1, DIR_FANOUT),
+                ('stp', [('o', 1, DIR_FANOUT)]),
                 ('nxt', [('i', 1, DIR_FANIN)]),
                 ('dir', [('i', 1, DIR_FANIN)]),
-                ('rst', 1, DIR_FANOUT),
+                ('rst', [('o', 1, DIR_FANOUT)]),
             ],
         )
 
         wrapper.connect(ulpi_data.i, ulpi.data.i)
         wrapper.connect(ulpi_data.o, ulpi.data.o)
         wrapper.connect(ulpi_data.oe, ulpi.data.oe)
 
-        wrapper.connect(pads.stp, ulpi.stp)
+        wrapper.connect(pads.stp, ulpi.stp.o)
         wrapper.connect(pads.nxt, ulpi.nxt.i)
         wrapper.connect(pads.dir, ulpi.dir.i)
-        wrapper.connect(ulpi_rst, ulpi.rst)
+        wrapper.connect(ulpi_rst, ulpi.rst.o)
 
         if hasattr(pads, 'clk'):
             wrapper.connect(pads.clk, ulpi.clk.i)

orbtrace/amaranth_glue/wrapper.py

@@ -1,5 +1,5 @@
 import amaranth
-from amaranth.hdl import ir
+from amaranth.hdl import _ast, _ir
 from amaranth.back import verilog
 
 import migen
@@ -45,8 +45,7 @@ def get_instance(self):
         connections = {}
 
         for m, n in self.connections:
-            module, name, *_ = self.amaranth_name_map[n]
-            direction = self.amaranth_dir_map[n]
+            name, direction = self.amaranth_name_map[n]
             s = f'{direction}_{name}'
 
             assert s not in connections, f'Signal {s} connected multiple times.'
@@ -58,22 +57,18 @@ def get_instance(self):
     def generate_verilog(self):
         ports = [n for m, n in self.connections]
 
-        fragment = ir.Fragment.get(self.m, None).prepare(ports = ports)
+        fragment = _ir.Fragment.get(self.m, None).prepare(ports = ports, hierarchy = (self.name,))
 
-        v, m = verilog.convert_fragment(fragment, name = self.name)
+        v, _name_map = verilog.convert_fragment(fragment, name = self.name)
+        netlist = _ir.build_netlist(fragment, name = self.name)
 
-        self.amaranth_dir_map = fragment.ports
-        self.amaranth_name_map = m
+        self.amaranth_name_map = _ast.SignalDict((sig, (name, 'o' if name in netlist.top.ports_o else 'i')) for name, sig, _ in fragment.ports)
 
-        for name, domain in fragment.domains.items():
+        for name, domain in fragment.fragment.domains.items():
             if domain.clk in self.amaranth_name_map:
                 self.amaranth_name_map[amaranth.ClockSignal(name)] = self.amaranth_name_map[domain.clk]
-            if domain.clk in self.amaranth_dir_map:
-                self.amaranth_dir_map[amaranth.ClockSignal(name)] = self.amaranth_dir_map[domain.clk]
             if domain.rst in self.amaranth_name_map:
                 self.amaranth_name_map[amaranth.ResetSignal(name)] = self.amaranth_name_map[domain.rst]
-            if domain.rst in self.amaranth_dir_map:
-                self.amaranth_dir_map[amaranth.ResetSignal(name)] = self.amaranth_dir_map[domain.rst]
 
         return v
 

orbtrace/dfu.py

@@ -136,6 +136,7 @@ def elaborate(self, platform):
         interface         = self.interface
         setup             = self.interface.setup
 
+        m.d.comb += interface.claim.eq((setup.recipient == USBRequestRecipient.INTERFACE) & (setup.index == self.if_num))
         m.d.usb += self.new_request.eq(0)
 
         with m.FSM(domain = 'usb'):

orbtrace/power/usb_handler.py

@@ -99,6 +99,8 @@ def elaborate(self, platform):
 
         setup = self.interface.setup
 
+        m.d.comb += self.interface.claim.eq((setup.recipient == USBRequestRecipient.INTERFACE) & (setup.index[:8] == self.if_num))
+
         with m.FSM(domain = 'usb'):
             with m.State('IDLE'):
                 self.transition(m)

orbtrace/trace/usb_handler.py

@@ -82,6 +82,8 @@ def elaborate(self, platform):
 
         setup = self.interface.setup
 
+        m.d.comb += self.interface.claim.eq((setup.recipient == USBRequestRecipient.INTERFACE) & ((setup.index[:8] == self.if_num) | (setup.index[:8] == self.proxy_if_num)))
+
         with m.FSM(domain = 'usb'):
             with m.State('IDLE'):
                 self.transition(m)

orbtrace/usb_mem_bridge.py

@@ -108,7 +108,7 @@ def elaborate(self, platform):
         setup             = self.interface.setup
 
         with m.If((setup.type == USBRequestType.VENDOR) & (setup.recipient == 3) & (setup.request == 0)):
-
+            m.d.comb += interface.claim.eq(1)
             address = Cat(setup.value, setup.index)
 
 

orbtrace/usb_serialnumber.py

@@ -75,14 +75,16 @@ def elaborate(self, platform):
 
         setup = self.interface.setup
 
+        get_descriptor = \
+            (setup.type == USBRequestType.STANDARD) & \
+            (setup.recipient == USBRequestRecipient.DEVICE) & \
+            (setup.request == USBStandardRequests.GET_DESCRIPTOR) & \
+            (setup.value == (DescriptorTypes.STRING << 8) | self.idx)
+
+        m.d.comb += self.interface.claim.eq(get_descriptor)
+
         with m.FSM(domain = 'usb'):
             with m.State('IDLE'):
-                get_descriptor = \
-                    (setup.type == USBRequestType.STANDARD) & \
-                    (setup.recipient == USBRequestRecipient.DEVICE) & \
-                    (setup.request == USBStandardRequests.GET_DESCRIPTOR) & \
-                    (setup.value == (DescriptorTypes.STRING << 8) | self.idx)
-
                 with m.If(setup.received & get_descriptor):
                     m.next = 'GET_DESCRIPTOR'