deps: Update to LiteX 2023.12 and Amaranth 0.4.0.

zyp · zyp · commit 2a8a2b7e9923 · 2024-01-13T11:40:13.000+01:00
diff --git a/.gitmodules b/.gitmodules
@@ -1,9 +1,6 @@
 [submodule "deps/amaranth"]
 	path = deps/amaranth
 	url = https://github.com/amaranth-lang/amaranth.git
-[submodule "deps/amaranth-boards"]
-	path = deps/amaranth-boards
-	url = https://github.com/amaranth-lang/amaranth-boards.git
 [submodule "deps/python-usb-protocol"]
 	path = deps/python-usb-protocol
 	url = https://github.com/usb-tools/python-usb-protocol.git
diff --git a/deps/amaranth b/deps/amaranth
@@ -1 +1 @@
-Subproject commit 85d56a74a595bac5b4423ace5462bc7452cfacbb
+Subproject commit a2f3c544eef8d55f29f115663eb33a467cc01178
diff --git a/deps/amaranth-boards b/deps/amaranth-boards
diff --git a/deps/litespi b/deps/litespi
@@ -1 +1 @@
-Subproject commit 7d32810ee05eb96e5cf4152483a3e1e501f9113c
+Subproject commit 96de7992df8c26d15b7bf698f615de00a18d55d3
diff --git a/deps/litex b/deps/litex
@@ -1 +1 @@
-Subproject commit 2b6fcf0b90a2c46df482260b7584d135373d73c2
+Subproject commit 67cfcadf7933ec6a6e75735e340c153fe4ca8480
diff --git a/deps/luna b/deps/luna
@@ -1 +1 @@
-Subproject commit 43247ef3ab25e1855a781ec280963b7a299f546c
+Subproject commit 76d2eed69fc59355621f4c4c812b62994bd945b0
diff --git a/deps/migen b/deps/migen
@@ -1 +1 @@
-Subproject commit ac703010eaa06ac9b6e32f97c6fa98b15de22b31
+Subproject commit 50934ad10a87ade47219b796535978b9bdf24023
diff --git a/deps/pythondata-cpu-vexriscv b/deps/pythondata-cpu-vexriscv
@@ -1 +1 @@
-Subproject commit cdfb2306087a680df65153760fd41002e316ad30
+Subproject commit 03d8c47e49872e3db7be5a9a04e7cd74021c41f1
diff --git a/orbtrace/debug/cmsis_dap.py b/orbtrace/debug/cmsis_dap.py
@@ -665,7 +665,7 @@ def RESP_Transfer_Process(self, m):
                 with m.If(self.streamOut.valid & self.streamOut.ready):
                     m.d.sync+=[
                         # Beware, state used to select byte in word construction
-                        self.tfrData.word_select(self.tfr_txb.bit_select(0,3)-2,8).eq(self.streamOut.payload),
+                        self.tfrData.word_select((self.tfr_txb.bit_select(0,3)-2).as_unsigned(),8).eq(self.streamOut.payload),
                         self.tfr_txb.eq(self.tfr_txb+1)
                     ]
 
@@ -747,7 +747,7 @@ def RESP_Transfer_Process(self, m):
             with m.Case(10,11,12):
                 with m.If(self.streamIn.ready):
                     m.d.sync += [
-                        self.streamIn.payload.eq(self.txBlock.word_select(self.tfr_txb-10,8)),
+                        self.streamIn.payload.eq(self.txBlock.word_select((self.tfr_txb-10).as_unsigned(),8)),
                         self.streamIn.valid.eq(1),
                         self.tfr_txb.eq(self.tfr_txb+1),
                         self.streamIn.last.eq(self.isV2 & (self.tfr_txb==12) & (self.tfrram.adr==0))
@@ -941,7 +941,7 @@ def RESP_Transfer_Complete(self, m):
                 with m.If(self.streamIn.ready & self.streamIn.valid):
                     m.d.sync += [
                         self.txb.eq(self.txb+1),
-                        self.streamIn.payload.eq(self.tfrram.dat_r.word_select(self.txb-2,8)),
+                        self.streamIn.payload.eq(self.tfrram.dat_r.word_select((self.txb-2).as_unsigned(),8)),
                         # 5 because of pipeline
                         self.streamIn.last.eq(self.isV2 & (~self.transferCCount.bool()) & (self.txb==5)),
                         self.streamIn.valid.eq(self.txb!=6)
diff --git a/orbtrace/microsoft_wcid/luna/gateware/usb/requests/windows/descriptorSet.py b/orbtrace/microsoft_wcid/luna/gateware/usb/requests/windows/descriptorSet.py
@@ -223,7 +223,7 @@ def elaborate(self, platform) -> Module:
 				m.d.comb += [
 					self.tx.valid.eq(1),
 					readPort.addr.eq(descriptorDataBaseAddress + wordInStream),
-					self.tx.payload.eq(readPort.data.word_select(3 - byteInStream, 8)),
+					self.tx.payload.eq(readPort.data.word_select(~byteInStream, 8)),
 					self.tx.first.eq(onFirstPacket),
 					self.tx.last.eq(onLastPacket),
 				]
diff --git a/orbtrace/platforms/orbtrace_mini.py b/orbtrace/platforms/orbtrace_mini.py
@@ -3,6 +3,7 @@
 from litex.build.openfpgaloader import OpenFPGALoader
 
 from litex.soc.cores.bitbang import I2CMaster
+from litex.soc.integration.soc import SoCRegion
 
 from ..crg_ecp5 import CRG
 
@@ -189,7 +190,7 @@ def add_platform_specific(self, soc):
 
         soc.submodules.hyperram = cdr(HyperRAM(pads))
         soc.add_csr('hyperram')
-        soc.register_mem('hyperram', soc.mem_map.get('hyperram', 0x20000000), soc.hyperram.bus, size = 0x800000)
+        soc.bus.add_slave('hyperram', soc.hyperram.bus, SoCRegion(origin = soc.mem_map.get('hyperram', 0x20000000), size = 0x800000))
 
         soc.comb += pads.rst_n.eq(1)
 
diff --git a/orbtrace/usb_serialnumber.py b/orbtrace/usb_serialnumber.py
@@ -24,7 +24,7 @@ def handle_get_descriptor(self, m, max_length):
         pos = Signal(range(0, self.data_length))
         data = Signal(8)
 
-        nibble_sel = (self.data_length - 1 - pos) >> 1
+        nibble_sel = (self.data_length - 1 - pos).as_unsigned() >> 1
         nibble = self.serial.word_select(nibble_sel, 4)
 
         with m.If(pos == 0):

Original file line number	Diff line number	Diff line change
`@@ -223,7 +223,7 @@ def elaborate(self, platform) -> Module:`
`223`	`223`	`m.d.comb += [`
`224`	`224`	`self.tx.valid.eq(1),`
`225`	`225`	`readPort.addr.eq(descriptorDataBaseAddress + wordInStream),`
`226`		`- self.tx.payload.eq(readPort.data.word_select(3 - byteInStream, 8)),`
	`226`	`+ self.tx.payload.eq(readPort.data.word_select(~byteInStream, 8)),`
`227`	`227`	`self.tx.first.eq(onFirstPacket),`
`228`	`228`	`self.tx.last.eq(onLastPacket),`
`229`	`229`	`]`