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    • fpga_project_sp26

      Public template
      SystemVerilog
      0000Updated Apr 24, 2026Apr 24, 2026
    • asic_project_sp26

      Public template
      C
      0000Updated Apr 10, 2026Apr 10, 2026
    • fpga-labs-sp26

      Public template
      SystemVerilog
      0000Updated Feb 24, 2026Feb 24, 2026
    • asic-labs-sp26

      Public template
      SystemVerilog
      0100Updated Feb 20, 2026Feb 20, 2026
    • fpga_project_fa25

      Public template
      Verilog
      1000Updated Dec 12, 2025Dec 12, 2025
    • asic_project_fa25

      Public template
      C
      0000Updated Nov 7, 2025Nov 7, 2025
    • fpga-labs-fa25

      Public template
      Verilog
      1000Updated Sep 26, 2025Sep 26, 2025
    • asic-labs-fa25

      Public template
      Verilog
      3000Updated Sep 26, 2025Sep 26, 2025
    • asic_project_sp25

      Public template
      C
      1000Updated Apr 28, 2025Apr 28, 2025
    • fpga_project_sp25

      Public template
      Verilog
      0400Updated Apr 18, 2025Apr 18, 2025
    • fpga-labs-sp25

      Public template
      Verilog
      0100Updated Feb 22, 2025Feb 22, 2025
    • asic-labs-sp25

      Public template
      Verilog
      0000Updated Feb 21, 2025Feb 21, 2025
    • fpga_project_fa24

      Public template
      Verilog
      0000Updated Nov 19, 2024Nov 19, 2024
    • asic_project_fa24

      Public template
      C
      1000Updated Oct 19, 2024Oct 19, 2024
    • fpga-labs-fa24

      Public template
      Verilog
      0000Updated Oct 11, 2024Oct 11, 2024
    • asic-labs-fa24

      Public template
      Verilog
      0100Updated Oct 11, 2024Oct 11, 2024
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