All

28 repositories

vyges-rv-dbg-tlul
Public
RISC-V Debug Module with TL-UL bus (private author repo). Public mirror at vyges-ip/vyges-rv-dbg-tlul.
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Apr 26, 2026Apr 26, 2026
vyges-edge-sensor-soc
Public
Vyges Edge Sensor SoC — Hardware-accelerated vibration monitoring on Sky130A. ChipFoundry Reference Application Design Contest entry.
asic fft soc
asic fft soc risc-v caravel openlane sky130 vibration-monitoring chipfoundry
Verilog
•
Apache License 2.0
•0•0•0•0•Updated Apr 25, 2026Apr 25, 2026
fast-fourier-transform-ip
Public
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, AP…
asic fpga pipeline
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip
SystemVerilog
•
Apache License 2.0
•1•0•0•0•Updated Apr 24, 2026Apr 24, 2026
vyges-rv-plic-lite
Public
Lightweight RISC-V PLIC with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Apr 24, 2026Apr 24, 2026
vyges-spi-host-lite
Public
Lightweight SPI master controller with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Apr 24, 2026Apr 24, 2026
tlul-apb-adapter
Public
Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.
hardware systemverilog risc-v
hardware systemverilog risc-v verilator amba apb tilelink ibex bus-adapter opentitan
SystemVerilog
•
Other
•0•0•0•0•Updated Apr 24, 2026Apr 24, 2026
vyges-metadata-spec
Public
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
metadata standards specification
metadata standards specification hardware-ip vyges
HTML
•
Other
•0•0•0•0•Updated Apr 23, 2026Apr 23, 2026
metadata-scorer-action
Public
Score a vyges-metadata.json against the Vyges integration-readiness rubric (0-100) and gate CI when below a threshold.
Python
•
Apache License 2.0
•0•0•0•0•Updated Apr 13, 2026Apr 13, 2026
vyges-pinmux-lite
Public
Lightweight pin multiplexer with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Mar 29, 2026Mar 29, 2026
vyges-clkmgr-lite
Public
Lightweight clock manager with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Mar 29, 2026Mar 29, 2026
vyges-gpio-lite
Public
Lightweight 32-pin GPIO controller with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Mar 29, 2026Mar 29, 2026
vyges-rstmgr-lite
Public
Lightweight reset manager with native TL-UL slave interface
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Mar 29, 2026Mar 29, 2026
32bit-risc-core
Public
Vyges 32-bit RISC Core — 5-stage pipelined processor with AXI-Lite interfaces, branch prediction, complex multiplier. Designed using the Vyges AI platform.
asic fpga pipeline
asic fpga pipeline processor systemverilog risc 32-bit branch-predictor axi-lite sky130
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Mar 23, 2026Mar 23, 2026
mlow-codec-ip
Public
A hardware implementation of Meta's MLow audio codec, delivering 2x better quality than Opus at 6kbps while maintaining 10% lower computational complexity. Opti…
Python
•
Apache License 2.0
•0•0•0•0•Updated Mar 16, 2026Mar 16, 2026
vybox-lite
Public template
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges
JavaScript
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Apache License 2.0
•0•1•0•0•Updated Feb 20, 2026Feb 20, 2026
xilinx-tools
Public template
Container infra to build and use Xilinx tools
Shell
•
Other
•0•0•0•0•Updated Feb 16, 2026Feb 16, 2026
vyges-ip-template
Public template
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
template opensource asic
template opensource asic hardware systemverilog ip-core openlane hardware-ip vyges silicon-design
Python
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Apache License 2.0
•0•13•0•0•Updated Dec 25, 2025Dec 25, 2025
programmable-adc
Public
Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.
verification adc systemverilog
verification adc systemverilog spectre cadence mixed-signal virtuoso behavioral-modeling analog-digital-converter vyges-ip
SystemVerilog
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Apache License 2.0
•0•0•0•0•Updated Dec 22, 2025Dec 22, 2025
spi-controller
Public
SPI master controller with APB interface, multi-mode support (all SPI modes), configurable FIFO, and interrupt features for ASIC/FPGA integration.
C++
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Apache License 2.0
•0•0•0•0•Updated Oct 8, 2025Oct 8, 2025
uart-controller
Public
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive v…
asic uart systemverilog
asic uart systemverilog verilator apb cocotb openlane sky130 hardware-ip vyges
SystemVerilog
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Apache License 2.0
•0•0•0•0•Updated Oct 8, 2025Oct 8, 2025
sd-card-controller-ip
Public
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Oct 8, 2025Oct 8, 2025
pwm-controller
Public
Configurable PWM controller with multiple channels and precise frequency control
SystemVerilog
•
Apache License 2.0
•0•0•0•0•Updated Oct 8, 2025Oct 8, 2025
lyra-vqdq-chiplet-ip
Public
Lyra Codec - VQDQ
Python
•
Apache License 2.0
•0•1•0•0•Updated Oct 8, 2025Oct 8, 2025
hilbert-transformer
Public
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature sign…
dsp hardware-ip vyges
dsp hardware-ip vyges
SystemVerilog
•
Apache License 2.0
•1•2•0•0•Updated Oct 8, 2025Oct 8, 2025
full-adder-ip
Public
A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes co…
systemverilog half-adder full-adder
systemverilog half-adder full-adder vyges vyges-ip
Python
•
Apache License 2.0
•0•0•0•0•Updated Oct 8, 2025Oct 8, 2025
.github
Public
0•0•0•0•Updated Aug 16, 2025Aug 16, 2025
vyges
Public
0•0•0•0•Updated Jul 8, 2025Jul 8, 2025
community
Public
🏗️ Central hub for Vyges community discussions, issues, feature requests, and collaboration
support open-source community
support open-source community documentation asic fpga discussions semiconductor metadata-standards chip-design
0•0•0•0•Updated Jul 8, 2025Jul 8, 2025

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vyges

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All

28 repositories

vyges-rv-dbg-tlul

vyges-edge-sensor-soc

fast-fourier-transform-ip

vyges-rv-plic-lite

vyges-spi-host-lite

tlul-apb-adapter

vyges-metadata-spec

metadata-scorer-action

vyges-pinmux-lite

vyges-clkmgr-lite

vyges-gpio-lite

vyges-rstmgr-lite

32bit-risc-core

mlow-codec-ip

vybox-lite

xilinx-tools

vyges-ip-template

programmable-adc

spi-controller

uart-controller

sd-card-controller-ip

pwm-controller

lyra-vqdq-chiplet-ip

hilbert-transformer

full-adder-ip

.github

vyges

community

All

All

Repositories list

28 repositories