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DanielKellerMDanielKellerM
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test: add standalone croc_idma testbench with DPI-C HAL bridge
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‎.gitignore‎

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.bender
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tmp
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*.log
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*.so

‎Bender.yml‎

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- rtl/test/croc_vip.sv
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- rtl/test/tb_croc_soc.sv
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- target: any(simulation, verilator)
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files:
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- rtl/obi/test/obi_sim_mem.sv
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- rtl/test/idma/tb_croc_idma_pkg.sv
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- rtl/test/idma/croc_idma_drv_if.sv
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- rtl/test/idma/croc_idma_base.sv
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- rtl/test/idma/tb_croc_idma.sv
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- target: genesys2
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files:
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- xilinx/hw/croc_xilinx.sv
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upstream: { git: "https://github.com/pulp-platform/obi.git", rev: "6a724da5c8d6412b88b6948746e04c1adf39d017" } # newest (0.1.7+)
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patch_dir: "rtl/.patches/obi"
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exclude_from_upstream:
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- "src/test"
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- "src/test/obi_test.sv"
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- "src/test/obi_asserter.sv"
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- "src/test/tb_obi_xbar.sv"
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- "src/test/tb_obi_atop_resolver.sv"
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- "src/test/atop_golden_mem_pkg.sv"
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mapping:
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- { from: 'src/', to: '', patch_dir: 'src/' }
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- { from: 'src/test/obi_sim_mem.sv', to: 'test/obi_sim_mem.sv', patch_dir: 'test/' }
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- { from: 'include/obi', to: 'include/obi', patch_dir: 'include/' }
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- { from: 'Bender.yml', to: 'Bender.yml', patch_dir: '' }
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- { from: 'Readme.md', to: 'Readme.md', patch_dir: '' }

‎rtl/idma/README.md‎

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Home of the iDMA - a modular, parametrizable, and highly flexible *Data Movement Accelerator (DMA)*
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architecture targeting a wide range of platforms from ultra-low power edge nodes to high-performance
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computing systems. iDMA is part of the [PULP (Parallel Ultra-Low-Power) platform](https://pulp-platform.org/),
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computing systems.
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---
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## Croc iDMA Standalone Testbench
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The `croc_idma` wrapper (`croc_idma.sv`) can be tested standalone, without running the full Croc SoC.
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The testbench uses DPI-C to bridge the **same C HAL functions** used by the software SDK
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(`sw/lib/src/idma.c`) into SystemVerilog, driving real OBI bus transactions on the DUT.
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### Prerequisites
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- QuestaSim (tested with 2025.3)
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- GCC (host compiler, for DPI shared library)
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- [Bender](https://github.com/pulp-platform/bender) (dependency manager)
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### Quick Start
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From the repository root:
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```sh
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# 1. Compile all RTL
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cd vsim
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./run_vsim.sh --flist
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./run_vsim.sh --build
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# 2. Build the DPI shared library
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gcc -shared -fPIC -o dpi_idma.so \
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-I$(questa-2025.3 vsim -version 2>&1 | head -1 > /dev/null; echo /usr/pack/questa-2025.3-dz/questasim/include) \
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-I../rtl/test/idma/dpi \
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../rtl/test/idma/dpi/idma_hal_dpi.c \
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../rtl/test/idma/dpi/test_idma_dpi.c
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# 3. Run the standalone iDMA testbench
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questa-2025.3 vsim -c tb_croc_idma -t 1ns \
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-sv_lib ./dpi_idma \
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-suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386 \
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-do "run -a; quit"
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```
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If `QUESTA_HOME` is set, replace the `-I` path with `-I${QUESTA_HOME}/include`.
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### What the Tests Cover
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| # | Test | Description |
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|---|------|-------------|
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| 1 | Register read/write | Write and readback all DMA config registers + ND enable bit |
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| 2 | 1D memcpy (16B) | Basic 4-word copy, matches `sw/test/test_idma.c` |
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| 3 | 2D transfer | 2 rows of 8 bytes, equal strides |
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| 4 | Large 1D memcpy (256B) | Exercises burst/legalizer paths |
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| 5 | Back-to-back transfers | Two sequential transfers, verifies job ID increment |
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| 6 | Non-aligned length (7B) | Odd byte count through the hardware legalizer |
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| 7 | 2D scatter/gather | Different src/dst strides (32 vs 8), 4 rows |
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| 8 | IRQ / busy signals | Verifies `busy_o` asserted during transfer, deasserted after |
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### Architecture
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```
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test_idma_dpi.c C test (8 test cases)
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|
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idma_hal_dpi.c C HAL (same API as sw/lib/src/idma.c)
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|
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dpi_bridge.h reg_write32/reg_read32 wrappers
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| (DPI export tasks)
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tb_croc_idma.sv SV top: DPI exports → OBI driver → DUT
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|
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croc_idma_base.sv Base harness: clock, reset, DUT, 2x obi_sim_mem
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```
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### File Overview
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```
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rtl/test/idma/
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├── tb_croc_idma_pkg.sv Timing params, register offsets, memory base addresses
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├── croc_idma_drv_if.sv OBI config port driver (procedural tasks)
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├── croc_idma_base.sv Base harness (clock, DUT, read/write sim memories)
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├── tb_croc_idma.sv Top-level TB with DPI imports/exports
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└── dpi/
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├── dpi_bridge.h DPI-C function declarations + convenience wrappers
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├── idma_hal_dpi.c iDMA HAL using DPI MMIO (replaces sw/lib/src/idma.c)
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└── test_idma_dpi.c Test entry point called from SV
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```
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### Adding New Tests
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Add new test functions in `test_idma_dpi.c` following the existing pattern:
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1. Pre-load source memory with `dpi_src_mem_write8()` / `dpi_src_mem_write32()`
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2. Call HAL functions (`idma_memcpy`, `idma_memcpy_2d`, or individual register setters)
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3. Verify destination memory with `dpi_dst_mem_read8()` / `dpi_dst_mem_read32()`
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4. Use `CHECK_ASSERT(id, condition)` for pass/fail — the assert ID is the return code on failure
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5. Register the new test in `run_idma_test()`
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Rebuild only the DPI library after changing C files (no SV recompile needed):
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```sh
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gcc -shared -fPIC -o dpi_idma.so -I${QUESTA_HOME}/include -I../rtl/test/idma/dpi \
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../rtl/test/idma/dpi/idma_hal_dpi.c ../rtl/test/idma/dpi/test_idma_dpi.c
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```
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--- iDMA is part of the [PULP (Parallel Ultra-Low-Power) platform](https://pulp-platform.org/),
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where it is used as a cluster level DMA in the [Snitch Cluster](https://github.com/pulp-platform/snitch)
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and in the [PULP Cluster](https://github.com/pulp-platform/pulp).
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‎rtl/obi/test/obi_sim_mem.sv‎

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// Copyright 2023 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
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module obi_sim_mem import obi_pkg::*; #(
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parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
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parameter type obi_req_t = logic,
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parameter type obi_rsp_t = logic,
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parameter type obi_r_chan_t = logic,
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parameter bit WarnUninitialized = 1'b0,
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parameter bit ClearErrOnAccess = 1'b0,
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parameter time ApplDelay = 0ps,
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parameter time AcqDelay = 0ps
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) (
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input logic clk_i,
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input logic rst_ni,
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input obi_req_t obi_req_i,
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output obi_rsp_t obi_rsp_o,
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output logic mon_valid_o,
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output logic mon_we_o,
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output logic [ ObiCfg.AddrWidth-1:0] mon_addr_o,
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output logic [ ObiCfg.DataWidth-1:0] mon_wdata_o,
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output logic [ObiCfg.DataWidth/8-1:0] mon_be_o,
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output logic [ ObiCfg.IdWidth-1:0] mon_id_o
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);
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if (ObiCfg.OptionalCfg.UseAtop) $error("Please use an ATOP resolver before sim mem.");
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if (ObiCfg.Integrity) $error("Integrity not supported");
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if (ObiCfg.OptionalCfg.UseProt) $warning("Prot not checked!");
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if (ObiCfg.OptionalCfg.UseMemtype) $warning("Memtype not checked!");
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typedef logic [ObiCfg.AddrWidth-1:0] addr_t;
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obi_r_chan_t rsp_queue[$];
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logic [7:0] mem[addr_t];
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logic rsp_ready;
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if (ObiCfg.UseRReady) begin : gen_rready
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assign rsp_ready = obi_req_i.rready;
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end else begin : gen_no_rready
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assign rsp_ready = 1'b1;
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end
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logic mon_valid;
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logic mon_we;
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logic [ObiCfg.AddrWidth-1:0] mon_addr;
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logic [ObiCfg.DataWidth-1:0] mon_wdata;
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logic [ObiCfg.DataWidth/8-1:0] mon_be;
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logic [ObiCfg.IdWidth-1:0] mon_id;
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assign mon_we = obi_req_i.a.we;
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assign mon_addr = obi_req_i.a.addr;
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assign mon_wdata = obi_req_i.a.wdata;
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assign mon_be = obi_req_i.a.be;
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assign mon_id = obi_req_i.a.aid;
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initial begin
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fork
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// Request Handling
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forever begin
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// Start cycle
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@(posedge clk_i);
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#(ApplDelay);
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// Indicate ready
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obi_rsp_o.gnt = 1'b1;
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mon_valid = 1'b0;
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// End of cycle
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#(AcqDelay-ApplDelay);
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// If requesting
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if (obi_req_i.req) begin
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mon_valid = 1'b1;
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if (obi_req_i.a.we) begin
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automatic obi_r_chan_t write_rsp;
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// write memory
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for (int i = 0; i < ObiCfg.DataWidth/8; i++) begin
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if (obi_req_i.a.be[i]) begin
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mem[obi_req_i.a.addr+i] = obi_req_i.a.wdata[8*i+:8];
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end
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end
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// write response
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write_rsp = 'x;
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write_rsp.rid = obi_req_i.a.aid;
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write_rsp.err = 1'b0;
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write_rsp.r_optional = '0;
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rsp_queue.push_back(write_rsp);
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end else begin
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// read response
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automatic obi_r_chan_t read_rsp = 'x;
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if (!mem.exists(obi_req_i.a.addr)) begin
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if (WarnUninitialized) begin
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$warning("%t - Access to non-initialized address at 0x%016x by ID 0x%x.",
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$realtime, obi_req_i.a.addr, obi_req_i.a.aid);
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end
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end else begin
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for (int i = 0; i < ObiCfg.DataWidth/8; i++) begin
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read_rsp.rdata[8*i+:8] = mem[obi_req_i.a.addr+i];
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end
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end
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read_rsp.rid = obi_req_i.a.aid;
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read_rsp.err = 1'b0;
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read_rsp.r_optional = '0;
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rsp_queue.push_back(read_rsp);
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end
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end
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end
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// Response Handling
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forever begin
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// Start cycle
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@(posedge clk_i);
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#(ApplDelay);
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obi_rsp_o.rvalid = 1'b0;
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if (rsp_queue.size() != 0) begin
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obi_rsp_o.r = rsp_queue[0];
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obi_rsp_o.rvalid = 1'b1;
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// End of cycle
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#(AcqDelay-ApplDelay);
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if (rsp_ready) begin
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void'(rsp_queue.pop_front());
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end
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end
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end
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join
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end
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initial begin
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mon_valid_o = '0;
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mon_we_o = '0;
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mon_addr_o = '0;
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mon_wdata_o = '0;
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mon_be_o = '0;
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mon_id_o = '0;
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wait (rst_ni);
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forever begin
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@(posedge clk_i);
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mon_valid_o <= #(ApplDelay) mon_valid;
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mon_we_o <= #(ApplDelay) mon_we;
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mon_addr_o <= #(ApplDelay) mon_addr;
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mon_wdata_o <= #(ApplDelay) mon_wdata;
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mon_be_o <= #(ApplDelay) mon_be;
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mon_id_o <= #(ApplDelay) mon_id;
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end
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end
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endmodule
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`include "obi/typedef.svh"
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`include "obi/assign.svh"
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module obi_sim_mem_intf import obi_pkg::*; #(
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parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
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parameter bit WarnUninitialized = 1'b0,
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parameter bit ClearErrOnAccess = 1'b0,
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parameter time ApplDelay = 0ps,
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parameter time AcqDelay = 0ps
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) (
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input logic clk_i,
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input logic rst_ni,
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OBI_BUS.Subordinate obi_sbr,
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output logic mon_valid_o,
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output logic mon_we_o,
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output logic [ ObiCfg.AddrWidth-1:0] mon_addr_o,
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output logic [ ObiCfg.DataWidth-1:0] mon_wdata_o,
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output logic [ObiCfg.DataWidth/8-1:0] mon_be_o,
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output logic [ ObiCfg.IdWidth-1:0] mon_id_o
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);
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`OBI_TYPEDEF_ALL(obi, ObiCfg)
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obi_req_t obi_req;
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obi_rsp_t obi_rsp;
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`OBI_ASSIGN_TO_REQ(obi_req, obi_sbr, ObiCfg)
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`OBI_ASSIGN_FROM_RSP(obi_sbr, obi_rsp, ObiCfg)
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obi_sim_mem #(
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.ObiCfg (ObiCfg),
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.obi_req_t (obi_req_t),
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.obi_rsp_t (obi_rsp_t),
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.obi_r_chan_t (obi_r_chan_t),
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.WarnUninitialized(WarnUninitialized),
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.ClearErrOnAccess (ClearErrOnAccess),
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.ApplDelay (ApplDelay),
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.AcqDelay (AcqDelay)
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) i_obi_sim_mem (
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.clk_i,
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.rst_ni,
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.obi_req_i(obi_req),
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.obi_rsp_o(obi_rsp),
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.mon_valid_o,
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.mon_we_o,
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.mon_addr_o,
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.mon_wdata_o,
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.mon_be_o,
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.mon_id_o
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);
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endmodule

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