CHANGELOG.md

Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

v0.0.0

Added

• iDMA: integrated iDMA wrap supporting up to 3D transfers with 2 physical channels and parametric burst length

Fixed

• Testbench: fixed timeunit to ns and change clock to 500 MHz

[Unreleased]

Added

• Added CHANGELOG.md

Changed

• Align Bender.yml IPs to ips_list.yml
• Bump fpu_interco to unreleased version
• Bump riscv to cv32e40p for pulp_soc v3.0.0 compatibility
• Bump axi to v0.29.1
• Updated schematic in doc
• Changed tcdm_banks to tc_sram tech cell, remove explicit FPGA RAM instatiation. This is now supposed to be handled by tc_sram wrapping a Xilinx XPM.

Removed

Fixed

• ibex implementation
• ID compliance of tcdm_banks
• Correct AXI ID width for icache bus

[2.0.0] - 2021-05-20

• Initial version prior to Changelog