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Navaneeth-KunhiPurayilmattsini1
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spatz_decoder: fix mv instruction decoding
1 parent b4d8094 commit 183c190

4 files changed

Lines changed: 60 additions & 3 deletions

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hw/ip/spatz/src/spatz_decoder.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,7 @@ module spatz_decoder
786786
spatz_req.op_sld.insert = (func3 == OPIVI || func3 == OPIVX || func3 == OPMVX);
787787
spatz_req.op_sld.vmv = 1'b1;
788788
spatz_req.vs2 = spatz_req.vs1;
789-
spatz_req.use_vs2 = func3 != OPIVI || decoder_req_i.instr inside {riscv_instr::VMV_S_X};
789+
spatz_req.use_vs2 = (func3 == OPIVV);
790790
spatz_req.op_arith.is_scalar = decoder_req_i.instr inside {riscv_instr::VMV_S_X};
791791
end
792792

@@ -1110,7 +1110,7 @@ module spatz_decoder
11101110
spatz_req.rs1 = decoder_req_i.rs1;
11111111
spatz_req.use_vs1 = 1'b0;
11121112
spatz_req.vs2 = spatz_req.vs1;
1113-
spatz_req.use_vs2 = decoder_req_i.instr inside {riscv_instr::VFMV_S_F};
1113+
spatz_req.use_vs2 = 1'b0;
11141114
spatz_req.op_arith.is_scalar = decoder_req_i.instr inside {riscv_instr::VFMV_S_F};
11151115
end
11161116

sw/riscvTests/isa/macros/vector/vector_macros.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ int test_case;
149149
return; \
150150
} \
151151
} \
152-
printf("PASSED.\n"); \
152+
printf("[TC %d] PASSED.\n", casenum); \
153153
} while (0)
154154

155155
// Check the results against an in-memory vector of golden values

sw/riscvTests/isa/rv64uv/vfmv.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,12 +60,41 @@ void TEST_CASE1(void) {
6060
#endif
6161
};
6262

63+
void TEST_CASE2(void) {
64+
VSET(16, e16, m8);
65+
float fscalar_16;
66+
// -0.9380
67+
BOX_HALF_IN_FLOAT(fscalar_16, 0xbb81);
68+
VCLEAR(v8);
69+
asm volatile("vfmv.s.f v8, %[A]" ::[A] "f"(fscalar_16));
70+
VCMP_U16(4, v8, 0xbb81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
71+
72+
VSET(16, e32, m8);
73+
float fscalar_32;
74+
// -0.96056187
75+
BOX_FLOAT_IN_FLOAT(fscalar_32, 0xbf75e762);
76+
VCLEAR(v8);
77+
asm volatile("vfmv.s.f v8, %[A]" ::[A] "f"(fscalar_32));
78+
VCMP_U32(5, v8, 0xbf75e762, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
79+
80+
#if ELEN == 64
81+
VSET(16, e64, m8);
82+
double dscalar_64;
83+
// 0.9108707261227378
84+
BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
85+
VCLEAR(v8);
86+
asm volatile("vfmv.s.f v8, %[A]" ::[A] "f"(dscalar_64));
87+
VCMP_U64(6, v8, 0x3fed25da5d7296fe, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
88+
#endif
89+
};
90+
6391
int main(void) {
6492
INIT_CHECK();
6593
enable_vec();
6694
enable_fp();
6795

6896
TEST_CASE1();
97+
TEST_CASE2();
6998

7099
EXIT_CHECK();
71100
}

sw/riscvTests/isa/rv64uv/vmv.c

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,13 +98,41 @@ void TEST_CASE3() {
9898
#endif
9999
}
100100

101+
void TEST_CASE4 () {
102+
// Integer scalar move instructions
103+
uint32_t scalar = 0xdeadbeef;
104+
105+
VSET(16, e8, m8);
106+
VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
107+
asm volatile("vmv.s.x v8, %[a]" :: [a] "r"(scalar));
108+
VCMP_U8(13, v8, 0x000000ef, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
109+
110+
VSET(16, e16, m8);
111+
VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
112+
asm volatile("vmv.s.x v8, %[a]" :: [a] "r"(scalar));
113+
VCMP_U16(14, v8, 0x0000beef, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
114+
115+
VSET(16, e32, m8);
116+
VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
117+
asm volatile("vmv.s.x v8, %[a]" :: [a] "r"(scalar));
118+
VCMP_U32(15, v8, 0xdeadbeef, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
119+
120+
#if ELEN == 64
121+
VSET(16, e64, m8);
122+
VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
123+
asm volatile("vmv.s.x v8, %[a]" :: [a] "r"(scalar));
124+
VCMP_U64(16, v8, 0xffffffffdeadbeef, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
125+
#endif
126+
}
127+
101128
int main(void) {
102129
INIT_CHECK();
103130
enable_vec();
104131

105132
TEST_CASE1();
106133
TEST_CASE2();
107134
TEST_CASE3();
135+
TEST_CASE4();
108136

109137
EXIT_CHECK();
110138
}

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