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| 1 | +// Copyright 2020 ETH Zurich and University of Bologna. |
| 2 | +// Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | +// SPDX-License-Identifier: Apache-2.0 |
| 4 | + |
| 5 | +// Cluster configuration for a simple system. |
| 6 | +{ |
| 7 | + "cluster": { |
| 8 | + "mempool": 0, |
| 9 | + "boot_addr": 4096, // 0x1000 |
| 10 | + "cluster_base_addr": 1048576, // 0x100000 |
| 11 | + "cluster_base_offset": 0, // 0x0 |
| 12 | + "cluster_base_hartid": 0, |
| 13 | + "addr_width": 32, |
| 14 | + "data_width": 32, |
| 15 | + "id_width_in": 2, |
| 16 | + "id_width_out": 4, |
| 17 | + "user_width": 2, |
| 18 | + "cluster_default_axi_user": 1, |
| 19 | + "axi_cdc_enable": false, |
| 20 | + "tcdm": { |
| 21 | + "size": 128, |
| 22 | + "banks": 16, |
| 23 | + "misalign": true |
| 24 | + }, |
| 25 | + "cluster_periph_size": 64, // kB |
| 26 | + "dma_data_width": 256, |
| 27 | + "dma_axi_req_fifo_depth": 3, |
| 28 | + "dma_req_fifo_depth": 3, |
| 29 | + // Spatz parameters |
| 30 | + "vlen": 512, |
| 31 | + "n_fpu": 4, |
| 32 | + "n_ipu": 1, |
| 33 | + "spatz_fpu": true, |
| 34 | + "spatz_nports": 8, |
| 35 | + "double_bw": 1, |
| 36 | + "buf_fpu": 1, |
| 37 | + // Timing parameters |
| 38 | + "timing": { |
| 39 | + "lat_comp_fp32": 1, |
| 40 | + "lat_comp_fp64": 2, |
| 41 | + "lat_comp_fp16": 0, |
| 42 | + "lat_comp_fp16_alt": 0, |
| 43 | + "lat_comp_fp8": 0, |
| 44 | + "lat_comp_fp8_alt": 0, |
| 45 | + "lat_noncomp": 1, |
| 46 | + "lat_conv": 2, |
| 47 | + "lat_sdotp": 2, |
| 48 | + "fpu_pipe_config": "BEFORE", |
| 49 | + "xbar_latency": "CUT_ALL_PORTS", |
| 50 | + |
| 51 | + "register_core_req": true, |
| 52 | + "register_core_rsp": true, |
| 53 | + "register_offload_rsp": true |
| 54 | + }, |
| 55 | + "cores": [ |
| 56 | + // DMA core |
| 57 | + { |
| 58 | + "isa": "rv32imaf", |
| 59 | + "xdma": true, |
| 60 | + "xf16": true, |
| 61 | + "xf8": true, |
| 62 | + "xfdotp": true, |
| 63 | + "num_int_outstanding_loads": 1, |
| 64 | + "num_int_outstanding_mem": 4, |
| 65 | + "num_spatz_outstanding_loads": 4, |
| 66 | + "num_dtlb_entries": 1, |
| 67 | + "num_itlb_entries": 1 |
| 68 | + }, |
| 69 | + |
| 70 | + // Compute core |
| 71 | + { |
| 72 | + "isa": "rv32imaf", |
| 73 | + "xf16": true, |
| 74 | + "xf8": true, |
| 75 | + "xfdotp": true, |
| 76 | + "xdma": false, |
| 77 | + "num_int_outstanding_loads": 1, |
| 78 | + "num_int_outstanding_mem": 4, |
| 79 | + "num_spatz_outstanding_loads": 4, |
| 80 | + "num_dtlb_entries": 1, |
| 81 | + "num_itlb_entries": 1 |
| 82 | + } |
| 83 | + ], |
| 84 | + "icache": { |
| 85 | + "size": 4, // total instruction cache size in kByte |
| 86 | + "ways": 2, // number of ways |
| 87 | + "cacheline": 256 // word size in bits |
| 88 | + } |
| 89 | + }, |
| 90 | + |
| 91 | + "dram": { |
| 92 | + // 0x8000_0000 |
| 93 | + "address": 2147483648, |
| 94 | + // 0x8000_0000 |
| 95 | + "length": 2147483648 |
| 96 | + }, |
| 97 | + |
| 98 | + "peripherals": { |
| 99 | + |
| 100 | + } |
| 101 | +} |
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