33 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
44 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
55 */
6-
76#ifndef _CAM_IFE_CSID_LITE17X_H_
87#define _CAM_IFE_CSID_LITE17X_H_
98
10- #include "cam_ife_csid_dev.h"
9+ #include <linux/module.h>
1110#include "cam_ife_csid_common.h"
1211#include "cam_ife_csid_hw_ver1.h"
12+ #include "cam_ife_csid_dev.h"
13+ #include "camera_main.h"
1314
1415#define CAM_CSID_LITE_DRV_NAME "csid_lite"
1516
16- static struct cam_ife_csid_ver1_path_reg_info
17- cam_ife_csid_lite_17x_rdi_0_reg_info = {
18-
17+ static struct cam_ife_csid_ver1_path_reg_info
18+ cam_ife_csid_lite_17x_rdi_0_reg_info = {
1919 .irq_status_addr = 0x30 ,
2020 .irq_mask_addr = 0x34 ,
2121 .irq_clear_addr = 0x38 ,
@@ -52,8 +52,11 @@ static struct cam_ife_csid_ver1_path_reg_info
5252 .timestamp_curr1_eof_addr = 0x2a4 ,
5353 .timestamp_prev0_eof_addr = 0x2a8 ,
5454 .timestamp_prev1_eof_addr = 0x2ac ,
55+ /* configurations */
5556 .byte_cntr_ping_addr = 0x2e0 ,
5657 .byte_cntr_pong_addr = 0x2e4 ,
58+ .crop_v_en_shift_val = 6 ,
59+ .crop_h_en_shift_val = 5 ,
5760 .halt_mode_internal = 0 ,
5861 .halt_mode_global = 1 ,
5962 .halt_mode_shift = 2 ,
@@ -63,17 +66,14 @@ static struct cam_ife_csid_ver1_path_reg_info
6366 .halt_cmd_shift = 0 ,
6467 .packing_fmt_shift_val = 30 ,
6568 .plain_fmt_shift_val = 10 ,
66- .crop_v_en_shift_val = 6 ,
67- .crop_h_en_shift_val = 5 ,
6869 .timestamp_en_shift_val = 2 ,
6970 .format_measure_en_shift_val = 1 ,
70- .fatal_err_mask = 0x4 ,
71+ .fatal_err_mask = 0x6004 ,
7172 .non_fatal_err_mask = 0xe000 ,
7273};
7374
74- static struct cam_ife_csid_ver1_path_reg_info
75- cam_ife_csid_lite_17x_rdi_1_reg_info = {
76-
75+ static struct cam_ife_csid_ver1_path_reg_info
76+ cam_ife_csid_lite_17x_rdi_1_reg_info = {
7777 .irq_status_addr = 0x40 ,
7878 .irq_mask_addr = 0x44 ,
7979 .irq_clear_addr = 0x48 ,
@@ -125,11 +125,12 @@ static struct cam_ife_csid_ver1_path_reg_info
125125 .crop_h_en_shift_val = 5 ,
126126 .timestamp_en_shift_val = 2 ,
127127 .format_measure_en_shift_val = 1 ,
128+ .fatal_err_mask = 0x4 ,
129+ .non_fatal_err_mask = 0xe000 ,
128130};
129131
130- static struct cam_ife_csid_ver1_path_reg_info
131- cam_ife_csid_lite_17x_rdi_2_reg_info = {
132-
132+ static struct cam_ife_csid_ver1_path_reg_info
133+ cam_ife_csid_lite_17x_rdi_2_reg_info = {
133134 .irq_status_addr = 0x50 ,
134135 .irq_mask_addr = 0x54 ,
135136 .irq_clear_addr = 0x58 ,
@@ -182,11 +183,12 @@ static struct cam_ife_csid_ver1_path_reg_info
182183 .crop_h_en_shift_val = 5 ,
183184 .timestamp_en_shift_val = 2 ,
184185 .format_measure_en_shift_val = 1 ,
186+ .fatal_err_mask = 0x4 ,
187+ .non_fatal_err_mask = 0xe000 ,
185188};
186189
187- static struct cam_ife_csid_ver1_path_reg_info
188- cam_ife_csid_lite_17x_rdi_3_reg_info = {
189-
190+ static struct cam_ife_csid_ver1_path_reg_info
191+ cam_ife_csid_lite_17x_rdi_3_reg_info = {
190192 .irq_status_addr = 0x60 ,
191193 .irq_mask_addr = 0x64 ,
192194 .irq_clear_addr = 0x68 ,
@@ -239,16 +241,16 @@ static struct cam_ife_csid_ver1_path_reg_info
239241 .crop_h_en_shift_val = 5 ,
240242 .timestamp_en_shift_val = 2 ,
241243 .format_measure_en_shift_val = 1 ,
244+ .fatal_err_mask = 0x4 ,
245+ .non_fatal_err_mask = 0xe000 ,
242246};
243247
244- static struct cam_ife_csid_csi2_rx_reg_info
245- cam_ife_csid_lite_17x_csi2_reg_info = {
246-
248+ static struct cam_ife_csid_csi2_rx_reg_info
249+ cam_ife_csid_lite_17x_csi2_reg_info = {
247250 .irq_status_addr = 0x20 ,
248251 .irq_mask_addr = 0x24 ,
249252 .irq_clear_addr = 0x28 ,
250253 .irq_set_addr = 0x2c ,
251-
252254 /*CSI2 rx control */
253255 .cfg0_addr = 0x100 ,
254256 .cfg1_addr = 0x104 ,
@@ -286,14 +288,23 @@ static struct cam_ife_csid_csi2_rx_reg_info
286288 .capture_cphy_pkt_dt_shift = 20 ,
287289 .capture_cphy_pkt_vc_shift = 26 ,
288290 .phy_num_mask = 0x3 ,
291+ .vc_mask = 0x7C00000 ,
292+ .dt_mask = 0x3f0000 ,
293+ .wc_mask = 0xffff ,
294+ .calc_crc_mask = 0xffff ,
295+ .expected_crc_mask = 0xffff ,
296+ .ecc_correction_shift_en = 0 ,
297+ .lane_num_shift = 0 ,
298+ .lane_cfg_shift = 4 ,
299+ .phy_type_shift = 24 ,
300+ .phy_num_shift = 20 ,
289301 .fatal_err_mask = 0x78000 ,
290302 .part_fatal_err_mask = 0x1801800 ,
291303 .non_fatal_err_mask = 0x380000 ,
292304};
293305
294-
295306static struct cam_ife_csid_ver1_tpg_reg_info
296- cam_ife_csid_lite_17x_tpg_reg_info = {
307+ cam_ife_csid_lite_17x_tpg_reg_info = {
297308 /*CSID TPG control */
298309 .ctrl_addr = 0x600 ,
299310 .vc_cfg0_addr = 0x604 ,
@@ -312,21 +323,20 @@ static struct cam_ife_csid_ver1_tpg_reg_info
312323 .cgen_n_xy_addr = 0x660 ,
313324 .cgen_n_y1_addr = 0x664 ,
314325 .cgen_n_y2_addr = 0x668 ,
315-
316326 /* configurations */
317327 .dtn_cfg_offset = 0xc ,
318328 .cgen_cfg_offset = 0x20 ,
319329 .cpas_ife_reg_offset = 0x28 ,
320330 .hbi = 0x740 ,
321331 .vbi = 0x3FF ,
322- .ctrl_cfg = 0x408007 ,
323332 .lfsr_seed = 0x12345678 ,
333+ .ctrl_cfg = 0x408007 ,
334+ .line_interleave_mode = 0x1 ,
324335 .color_bar = 1 ,
325336 .num_frames = 0 ,
326- .line_interleave_mode = 0x1 ,
337+ .num_active_dt = 0 ,
327338 .payload_mode = 0x8 ,
328339 .num_active_lanes_mask = 0x30 ,
329- .num_active_dt = 0 ,
330340 .fmt_shift = 16 ,
331341 .num_frame_shift = 16 ,
332342 .width_shift = 16 ,
@@ -338,10 +348,8 @@ static struct cam_ife_csid_ver1_tpg_reg_info
338348 .hbi_shift = 0 ,
339349};
340350
341-
342- static struct cam_ife_csid_ver1_common_reg_info
343- cam_csid_lite_17x_cmn_reg_info = {
344-
351+ static struct cam_ife_csid_ver1_common_reg_info
352+ cam_csid_lite_17x_cmn_reg_info = {
345353 .hw_version_addr = 0x0 ,
346354 .cfg0_addr = 0x4 ,
347355 .ctrl_addr = 0x8 ,
@@ -361,8 +369,7 @@ static struct cam_ife_csid_ver1_common_reg_info
361369 .version_incr = 0 ,
362370 .num_rdis = 4 ,
363371 .num_pix = 0 ,
364- .timestamp_strobe_val = 0x2 ,
365- .timestamp_stb_sel_shift_val = 0 ,
372+ .num_ppp = 0 ,
366373 .rst_sw_reg_stb = 1 ,
367374 .rst_hw_reg_stb = 0x1e ,
368375 .rst_sw_hw_reg_stb = 0x1f ,
@@ -381,7 +388,11 @@ static struct cam_ife_csid_ver1_common_reg_info
381388 .crop_line_end_mask = 0xffff ,
382389 .ipp_irq_mask_all = 0x7FFF ,
383390 .rdi_irq_mask_all = 0x7FFF ,
384- .ppp_irq_mask_all = 0xFFFF ,
391+ .ppp_irq_mask_all = 0x0 ,
392+ .measure_en_hbi_vbi_cnt_mask = 0xC ,
393+ .measure_pixel_line_en_mask = 0x3 ,
394+ .timestamp_strobe_val = 0x2 ,
395+ .timestamp_stb_sel_shift_val = 0 ,
385396 .format_measure_height_mask_val = 0xFFFF ,
386397 .format_measure_height_shift_val = 0x10 ,
387398 .format_measure_width_mask_val = 0xFFFF ,
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