adc: Flip SCK Polarity & Change CNVN timings

- To read the missed data bit in each transaction

Author: linuswck

adc.py

@@ -50,7 +50,7 @@ def __init__(self, pins, params):
         self.sdo2n = sdo2n = Signal()  # inverted input
         self.ddr_clk_synth = ddr_clk_synth = Signal(
             6, reset=0b000111
-        )  # signal to generate a 10ns period clock
+        )  # signal to generate a 4 ns * 3 = 12 ns period clock
 
         if pins != None:
             self.specials += [
@@ -59,7 +59,7 @@ def __init__(self, pins, params):
                 DifferentialOutput(~cnvn, pins.cnvn_n, pins.cnvn_p),  # swapped
                 DifferentialInput(pins.sdo_p[0], pins.sdo_n[0], sdo[0]),
                 DifferentialInput(pins.sdo_n[1], pins.sdo_p[1], sdo2n),  # swapped
-                DDROutput(ddr_clk_synth[1], ddr_clk_synth[0], sck, ClockSignal("sys")),
+                DDROutput(~ddr_clk_synth[1], ~ddr_clk_synth[0], sck, ClockSignal("sys")),
             ]
 
         self.comb += [

phaser.py

@@ -238,11 +238,11 @@ def __init__(self, platform):
             self.decoder.get("spi_datr", "read").eq(self.spi.reg.pdi),
         ]
 
-        # 32 ns t_cnvh, 12 ns t_conv/t_DCNVSCKL, 192 ns data transfer, 24 ns t_rtt/tDSCKLCNVH
+        # 32 ns t_cnvh, 16 ns t_conv/t_DCNVSCKL, 192 ns data transfer, 20 ns t_rtt/tDSCKLCNVH
         # Note that there is one extra cycle (4 ns) at the end of a transaction.
         # Total: 264 ns -> 3.788 MSps
         adc_parameters = AdcParams(
-            width=16, channels=2, lanes=2, t_cnvh=8, t_conv=3, t_rtt=6
+            width=16, channels=2, lanes=2, t_cnvh=8, t_conv=4, t_rtt=5
         )
 
         self.submodules.adc = adc = Adc(platform.request("adc"), adc_parameters)