fixup! net: cadence: macb: add EEE register definitions and capability flag

Add GEM_RXLPISBC (bit 27) interrupt bitfield definition for the RX LPI
Status Bit Change interrupt in ISR/IER/IDR/IMR registers.

Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>

Author: nbuchwitz

drivers/net/ethernet/cadence/macb.h

@@ -461,6 +461,8 @@
 #define MACB_PDRSFT_SIZE	1
 #define MACB_SRI_OFFSET		26 /* TSU Seconds Register Increment */
 #define MACB_SRI_SIZE		1
+#define GEM_RXLPISBC_OFFSET	27 /* RX LPI Status Bit Change */
+#define GEM_RXLPISBC_SIZE	1
 #define GEM_WOL_OFFSET		28 /* Enable wake-on-lan interrupt */
 #define GEM_WOL_SIZE		1