add Cortex-A72 Spectre v4 (CVE-2018-3639) mitigation

Author: lilyanatia

armstubs/Makefile

@@ -1,4 +1,4 @@
-BINS=armstub.bin armstub7.bin armstub8-32.bin armstub8-32-gic.bin armstub8.bin armstub8-gic.bin armstub8-gic-highperi.bin
+BINS=armstub.bin armstub7.bin armstub8-32.bin armstub8-32-gic.bin armstub8.bin armstub8-gic.bin armstub8-gic-highperi.bin armstub8-gic-spectrev4.bin
 
 CC8?=aarch64-linux-gnu-gcc
 LD8?=aarch64-linux-gnu-ld
@@ -26,6 +26,9 @@ clean :
 %8-gic-highperi.o: %8.S
 	$(CC8) -DGIC=1 -DHIGH_PERI=1 -DBCM2711=1 -c $< -o $@
 
+%8-gic-spectrev4.o: %8.S
+	$(CC8) -DGIC=1 -DSPECTRE_V4=1 -DBCM2711=1 -c $< -o $@
+
 %8-32.o: %7.S
 	$(CC7) -DBCM2710=1 -c $< -o $@
 
@@ -41,6 +44,9 @@ clean :
 %8-gic-highperi.elf: %8-gic-highperi.o
 	$(LD8) --section-start=.text=0 $< -o $@
 
+%8-gic-spectrev4.elf: %8-gic-spectrev4.o
+	$(LD8) --section-start=.text=0 $< -o $@
+
 %8.elf: %8.o
 	$(LD8) --section-start=.text=0 $< -o $@
 
@@ -53,6 +59,9 @@ clean :
 %8-gic-highperi.tmp: %8-gic-highperi.elf
 	$(OBJCOPY8) $< -O binary $@
 
+%8-gic-spectrev4.tmp: %8-gic-spectrev4.elf
+	$(OBJCOPY8) $< -O binary $@
+
 %8.tmp: %8.elf
 	$(OBJCOPY8) $< -O binary $@
 
@@ -75,7 +84,7 @@ clean :
 $(BIN2C): bin2c.c
 	gcc $< -o $@
 
-armstubs.h: armstub.C armstub7.C armstub8-32.C armstub8-32-gic.C armstub8.C armstub8-gic.C armstub8-gic-highperi.C
+armstubs.h: armstub.C armstub7.C armstub8-32.C armstub8-32-gic.C armstub8.C armstub8-gic.C armstub8-gic-highperi.C armstub8-gic-spectrev4.C
 	echo 'static const unsigned armstub[] = {' > $@
 	cat armstub.C >> $@
 	echo '};' >> $@
@@ -97,4 +106,7 @@ armstubs.h: armstub.C armstub7.C armstub8-32.C armstub8-32-gic.C armstub8.C arms
 	echo 'static const unsigned armstub8_gic_highperi[] = {' >> $@
 	cat armstub8-gic-highperi.C >> $@
 	echo '};' >> $@
+	echo 'static const unsigned armstub8_gic_spectrev4[] = {' >> $@
+	cat armstub8-gic-spectrev4.C >> $@
+	echo '};' >> $@
 

armstubs/armstub8.S

@@ -65,6 +65,9 @@
 #define SCR_VAL \
     (SCR_RW | SCR_HCE | SCR_SMD | SCR_RES1_5 | SCR_RES1_4 | SCR_NS)
 
+#define CPUACTLR_EL1		S3_1_C15_C2_0
+#define CPUACTLR_EL1_DLPS	BIT(55)
+
 #define CPUECTLR_EL1		S3_1_C15_C2_1
 #define CPUECTLR_EL1_SMPEN	BIT(6)
 
@@ -124,6 +127,12 @@ _start:
 	mov x0, #CPUECTLR_EL1_SMPEN
 	msr CPUECTLR_EL1, x0
 
+#ifdef SPECTRE_V4
+	/* mitigate Spectre v4 */
+	mov x0, #CPUACTLR_EL1_DLPS
+	msr CPUACTLR_EL1, x0
+#endif
+
 #ifdef GIC
         bl      setup_gic
 #endif