Skip to content

Commit eb35942

Browse files
racerxdlracerxdl
committed
[#860] device support: MH1903 Bootrom boot support
Implement complete peripherals for the MH1903 SoC: - QSPI: Quad SPI Flash controller with Renode SPI framework integration - OTP: One-Time Programmable memory controller - 10 control registers (CFG, CS, PROT, ADDR, PDATA, RO, ROLEN, RSVD, TIM, TIM_EN) - 2048 x 32-bit OTP data area - Proper reset values per MH1903 datasheet - GPIO: General Purpose I/O ports A-F - BSRR (Bit Set/Reset Register) implementation for atomic pin control - Full register definitions for ODR, IDR, PUPDR, etc. - Integration with Renode GPIO framework - UART: Universal Asynchronous Receiver/Transmitter (0-3) - Complete UART0-3 implementations with FIFO support - TX/RX callbacks for character transmission - Programmable baud rate via divisor latch - SYSCTRL: System Control peripheral - Clock gating control registers - Power management registers - System configuration registers
1 parent 26bb6ae commit eb35942

17 files changed

Lines changed: 4355 additions & 0 deletions

File tree

‎src/Emulator/Peripherals/Peripherals/Analog/MH1903_ADC.cs‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
using Antmicro.Renode.Core;
2+
using Antmicro.Renode.Core.Structure.Registers;
3+
4+
namespace Antmicro.Renode.Peripherals.Analog
5+
{
6+
public class MH1903_ADC : BasicDoubleWordPeripheral, IKnownSize
7+
{
8+
public MH1903_ADC(IMachine machine) : base(machine)
9+
{
10+
DefineRegisters();
11+
}
12+
13+
public GPIO IRQ { get; } = new GPIO();
14+
15+
public long Size => 0x100;
16+
17+
private void DefineRegisters()
18+
{
19+
// ADC_CR1 - Control Register 1 at 0x00
20+
Registers.ADC_CR1.Define(this, resetValue: 0x00000000)
21+
.WithValueField(0, 32, name: "adc_cr1");
22+
23+
// ADC_SR - Status Register at 0x04
24+
Registers.ADC_SR.Define(this, resetValue: 0x00000001)
25+
.WithFlag(0, FieldMode.Read, name: "adc_ready", valueProviderCallback: _ => true)
26+
.WithReservedBits(1, 31);
27+
28+
// ADC_FIFO - FIFO Register at 0x08
29+
Registers.ADC_FIFO.Define(this, resetValue: 0x00000000)
30+
.WithValueField(0, 32, name: "adc_fifo");
31+
32+
// ADC_DATA - Data Register at 0x0C
33+
Registers.ADC_DATA.Define(this, resetValue: 0x00000D70) // 3440 = ~4.2V
34+
.WithValueField(0, 16, FieldMode.Read, name: "adc_data",
35+
valueProviderCallback: _ => adcData);
36+
37+
// ADC_FIFO_FL - FIFO Level at 0x10
38+
Registers.ADC_FIFO_FL.Define(this, resetValue: 0x00000000)
39+
.WithValueField(0, 32, name: "adc_fifo_fl");
40+
41+
// ADC_FIFO_THR - FIFO Threshold at 0x14
42+
Registers.ADC_FIFO_THR.Define(this, resetValue: 0x00000000)
43+
.WithValueField(0, 32, name: "adc_fifo_thr");
44+
45+
// ADC_CR2 - Control Register 2 at 0x18
46+
Registers.ADC_CR2.Define(this, resetValue: 0x00000000)
47+
.WithValueField(0, 32, name: "adc_cr2");
48+
}
49+
50+
private readonly ushort adcData = 0x0D70; // 3440 = ~4.2V
51+
52+
private enum Registers : long
53+
{
54+
ADC_CR1 = 0x00,
55+
ADC_SR = 0x04,
56+
ADC_FIFO = 0x08,
57+
ADC_DATA = 0x0C,
58+
ADC_FIFO_FL = 0x10,
59+
ADC_FIFO_THR = 0x14,
60+
ADC_CR2 = 0x18,
61+
}
62+
}
63+
}

‎src/Emulator/Peripherals/Peripherals/Cache/MH1903_CACHE.cs‎

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,148 @@
1+
using Antmicro.Renode.Core;
2+
using Antmicro.Renode.Core.Structure.Registers;
3+
4+
namespace Antmicro.Renode.Peripherals.Cache
5+
{
6+
public class MH1903_CACHE : BasicDoubleWordPeripheral, IKnownSize
7+
{
8+
public MH1903_CACHE(IMachine machine) : base(machine)
9+
{
10+
DefineRegisters();
11+
}
12+
13+
public long Size => 0x80;
14+
15+
private void DefineRegisters()
16+
{
17+
// CACHE_I0 at offset 0x00
18+
Registers.CACHE_I0.Define(this, resetValue: 0x00000000)
19+
.WithValueField(0, 32, name: "cache_i0");
20+
21+
// CACHE_I1 at offset 0x04
22+
Registers.CACHE_I1.Define(this, resetValue: 0x00000000)
23+
.WithValueField(0, 32, name: "cache_i1");
24+
25+
// CACHE_I2 at offset 0x08
26+
Registers.CACHE_I2.Define(this, resetValue: 0x00000000)
27+
.WithValueField(0, 32, name: "cache_i2");
28+
29+
// CACHE_I3 at offset 0x0C
30+
Registers.CACHE_I3.Define(this, resetValue: 0x00000000)
31+
.WithValueField(0, 32, name: "cache_i3");
32+
33+
// CACHE_K0 at offset 0x10
34+
Registers.CACHE_K0.Define(this, resetValue: 0x00000000)
35+
.WithValueField(0, 32, name: "cache_k0");
36+
37+
// CACHE_K1 at offset 0x14
38+
Registers.CACHE_K1.Define(this, resetValue: 0x00000000)
39+
.WithValueField(0, 32, name: "cache_k1");
40+
41+
// CACHE_K2 at offset 0x18
42+
Registers.CACHE_K2.Define(this, resetValue: 0x00000000)
43+
.WithValueField(0, 32, name: "cache_k2");
44+
45+
// CACHE_K3 at offset 0x1C
46+
Registers.CACHE_K3.Define(this, resetValue: 0x00000000)
47+
.WithValueField(0, 32, name: "cache_k3");
48+
49+
// CACHE_CS at offset 0x20
50+
Registers.CACHE_CS.Define(this, resetValue: 0x00000000)
51+
.WithValueField(0, 32, name: "cache_cs");
52+
53+
// CACHE_REF at offset 0x24 - when written, gets cleared to 0
54+
Registers.CACHE_REF.Define(this, resetValue: 0x00000000)
55+
.WithValueField(0, 32, FieldMode.Write, name: "cache_ref",
56+
writeCallback: (_, __) => { /* Writing clears it, do nothing */ });
57+
58+
// Reserved area 0x28-0x3F (6 words)
59+
Registers.CACHE_RSVD0_0.Define(this)
60+
.WithReservedBits(0, 32);
61+
Registers.CACHE_RSVD0_1.Define(this)
62+
.WithReservedBits(0, 32);
63+
Registers.CACHE_RSVD0_2.Define(this)
64+
.WithReservedBits(0, 32);
65+
Registers.CACHE_RSVD0_3.Define(this)
66+
.WithReservedBits(0, 32);
67+
Registers.CACHE_RSVD0_4.Define(this)
68+
.WithReservedBits(0, 32);
69+
Registers.CACHE_RSVD0_5.Define(this)
70+
.WithReservedBits(0, 32);
71+
72+
// CACHE_CONFIG at offset 0x40
73+
Registers.CACHE_CONFIG.Define(this, resetValue: 0x00000000)
74+
.WithValueField(0, 32, name: "cache_config");
75+
76+
// Reserved area 0x44-0x73 (12 words)
77+
Registers.CACHE_RSVD1_0.Define(this)
78+
.WithReservedBits(0, 32);
79+
Registers.CACHE_RSVD1_1.Define(this)
80+
.WithReservedBits(0, 32);
81+
Registers.CACHE_RSVD1_2.Define(this)
82+
.WithReservedBits(0, 32);
83+
Registers.CACHE_RSVD1_3.Define(this)
84+
.WithReservedBits(0, 32);
85+
Registers.CACHE_RSVD1_4.Define(this)
86+
.WithReservedBits(0, 32);
87+
Registers.CACHE_RSVD1_5.Define(this)
88+
.WithReservedBits(0, 32);
89+
Registers.CACHE_RSVD1_6.Define(this)
90+
.WithReservedBits(0, 32);
91+
Registers.CACHE_RSVD1_7.Define(this)
92+
.WithReservedBits(0, 32);
93+
Registers.CACHE_RSVD1_8.Define(this)
94+
.WithReservedBits(0, 32);
95+
Registers.CACHE_RSVD1_9.Define(this)
96+
.WithReservedBits(0, 32);
97+
Registers.CACHE_RSVD1_10.Define(this)
98+
.WithReservedBits(0, 32);
99+
Registers.CACHE_RSVD1_11.Define(this)
100+
.WithReservedBits(0, 32);
101+
102+
// CACHE_SADDR at offset 0x74
103+
Registers.CACHE_SADDR.Define(this, resetValue: 0x00000000)
104+
.WithValueField(0, 32, name: "cache_saddr");
105+
106+
// CACHE_EADDR at offset 0x78
107+
Registers.CACHE_EADDR.Define(this, resetValue: 0x00000000)
108+
.WithValueField(0, 32, name: "cache_eaddr");
109+
}
110+
111+
private enum Registers : long
112+
{
113+
CACHE_I0 = 0x00,
114+
CACHE_I1 = 0x04,
115+
CACHE_I2 = 0x08,
116+
CACHE_I3 = 0x0C,
117+
CACHE_K0 = 0x10,
118+
CACHE_K1 = 0x14,
119+
CACHE_K2 = 0x18,
120+
CACHE_K3 = 0x1C,
121+
CACHE_CS = 0x20,
122+
CACHE_REF = 0x24,
123+
// Reserved 0x28-0x3F (6 words)
124+
CACHE_RSVD0_0 = 0x28,
125+
CACHE_RSVD0_1 = 0x2C,
126+
CACHE_RSVD0_2 = 0x30,
127+
CACHE_RSVD0_3 = 0x34,
128+
CACHE_RSVD0_4 = 0x38,
129+
CACHE_RSVD0_5 = 0x3C,
130+
CACHE_CONFIG = 0x40,
131+
// Reserved 0x44-0x73 (12 words)
132+
CACHE_RSVD1_0 = 0x44,
133+
CACHE_RSVD1_1 = 0x48,
134+
CACHE_RSVD1_2 = 0x4C,
135+
CACHE_RSVD1_3 = 0x50,
136+
CACHE_RSVD1_4 = 0x54,
137+
CACHE_RSVD1_5 = 0x58,
138+
CACHE_RSVD1_6 = 0x5C,
139+
CACHE_RSVD1_7 = 0x60,
140+
CACHE_RSVD1_8 = 0x64,
141+
CACHE_RSVD1_9 = 0x68,
142+
CACHE_RSVD1_10 = 0x6C,
143+
CACHE_RSVD1_11 = 0x70,
144+
CACHE_SADDR = 0x74,
145+
CACHE_EADDR = 0x78,
146+
}
147+
}
148+
}

0 commit comments

Comments
 (0)