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Merge pull request thesofproject#5426 from bardliao/merge/sound-upstream-20250523
Merge/sound upstream 20250523
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‎.mailmap‎

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@@ -102,6 +102,7 @@ Ard Biesheuvel <ardb@kernel.org> <ard.biesheuvel@linaro.org>
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Arnaud Patard <arnaud.patard@rtp-net.org>
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Arnd Bergmann <arnd@arndb.de>
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Arun Kumar Neelakantam <quic_aneela@quicinc.com> <aneela@codeaurora.org>
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Asahi Lina <lina+kernel@asahilina.net> <lina@asahilina.net>
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Ashok Raj Nagarajan <quic_arnagara@quicinc.com> <arnagara@codeaurora.org>
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Ashwin Chaugule <quic_ashwinc@quicinc.com> <ashwinc@codeaurora.org>
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Asutosh Das <quic_asutoshd@quicinc.com> <asutoshd@codeaurora.org>

‎Documentation/ABI/testing/sysfs-devices-system-cpu‎

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@@ -273,6 +273,60 @@ Description: Discover CPUs in the same CPU frequency coordination domain
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This file is only present if the acpi-cpufreq or the cppc-cpufreq
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drivers are in use.
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What: /sys/devices/system/cpu/cpuX/cpufreq/auto_select
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Date: May 2025
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Contact: linux-pm@vger.kernel.org
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Description: Autonomous selection enable
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Read/write interface to control autonomous selection enable
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Read returns autonomous selection status:
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0: autonomous selection is disabled
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1: autonomous selection is enabled
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Write 'y' or '1' or 'on' to enable autonomous selection.
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Write 'n' or '0' or 'off' to disable autonomous selection.
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This file is only present if the cppc-cpufreq driver is in use.
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What: /sys/devices/system/cpu/cpuX/cpufreq/auto_act_window
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Date: May 2025
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Contact: linux-pm@vger.kernel.org
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Description: Autonomous activity window
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This file indicates a moving utilization sensitivity window to
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the platform's autonomous selection policy.
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Read/write an integer represents autonomous activity window (in
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microseconds) from/to this file. The max value to write is
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1270000000 but the max significand is 127. This means that if 128
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is written to this file, 127 will be stored. If the value is
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greater than 130, only the first two digits will be saved as
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significand.
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Writing a zero value to this file enable the platform to
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determine an appropriate Activity Window depending on the workload.
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Writing to this file only has meaning when Autonomous Selection is
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enabled.
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This file is only present if the cppc-cpufreq driver is in use.
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What: /sys/devices/system/cpu/cpuX/cpufreq/energy_performance_preference_val
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Date: May 2025
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Contact: linux-pm@vger.kernel.org
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Description: Energy performance preference
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Read/write an 8-bit integer from/to this file. This file
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represents a range of values from 0 (performance preference) to
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0xFF (energy efficiency preference) that influences the rate of
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performance increase/decrease and the result of the hardware's
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energy efficiency and performance optimization policies.
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Writing to this file only has meaning when Autonomous Selection is
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enabled.
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This file is only present if the cppc-cpufreq driver is in use.
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What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
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Date: August 2008
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What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/gather_data_sampling
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/sys/devices/system/cpu/vulnerabilities/indirect_target_selection
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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/sys/devices/system/cpu/vulnerabilities/l1tf
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/sys/devices/system/cpu/vulnerabilities/mds

‎Documentation/ABI/testing/sysfs-driver-hid-appletb-kbd‎

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What: /sys/bus/hid/drivers/hid-appletb-kbd/<dev>/mode
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Date: September, 2023
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KernelVersion: 6.5
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Date: March, 2025
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KernelVersion: 6.15
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Contact: linux-input@vger.kernel.org
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Description:
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The set of keys displayed on the Touch Bar.

‎Documentation/admin-guide/hw-vuln/index.rst‎

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gather_data_sampling
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reg-file-data-sampling
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rsb
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indirect-target-selection

‎Documentation/admin-guide/hw-vuln/indirect-target-selection.rst‎

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.. SPDX-License-Identifier: GPL-2.0
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Indirect Target Selection (ITS)
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===============================
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ITS is a vulnerability in some Intel CPUs that support Enhanced IBRS and were
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released before Alder Lake. ITS may allow an attacker to control the prediction
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of indirect branches and RETs located in the lower half of a cacheline.
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ITS is assigned CVE-2024-28956 with a CVSS score of 4.7 (Medium).
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Scope of Impact
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---------------
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- **eIBRS Guest/Host Isolation**: Indirect branches in KVM/kernel may still be
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predicted with unintended target corresponding to a branch in the guest.
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- **Intra-Mode BTI**: In-kernel training such as through cBPF or other native
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gadgets.
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- **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
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branches may still be predicted with targets corresponding to direct branches
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executed prior to the IBPB. This is fixed by the IPU 2025.1 microcode, which
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should be available via distro updates. Alternatively microcode can be
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obtained from Intel's github repository [#f1]_.
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Affected CPUs
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-------------
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Below is the list of ITS affected CPUs [#f2]_ [#f3]_:
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======================== ============ ==================== ===============
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Common name Family_Model eIBRS Intra-mode BTI
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Guest/Host Isolation
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======================== ============ ==================== ===============
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SKYLAKE_X (step >= 6) 06_55H Affected Affected
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ICELAKE_X 06_6AH Not affected Affected
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ICELAKE_D 06_6CH Not affected Affected
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ICELAKE_L 06_7EH Not affected Affected
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TIGERLAKE_L 06_8CH Not affected Affected
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TIGERLAKE 06_8DH Not affected Affected
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KABYLAKE_L (step >= 12) 06_8EH Affected Affected
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KABYLAKE (step >= 13) 06_9EH Affected Affected
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COMETLAKE 06_A5H Affected Affected
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COMETLAKE_L 06_A6H Affected Affected
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ROCKETLAKE 06_A7H Not affected Affected
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======================== ============ ==================== ===============
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- All affected CPUs enumerate Enhanced IBRS feature.
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- IBPB isolation is affected on all ITS affected CPUs, and need a microcode
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update for mitigation.
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- None of the affected CPUs enumerate BHI_CTRL which was introduced in Golden
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Cove (Alder Lake and Sapphire Rapids). This can help guests to determine the
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host's affected status.
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- Intel Atom CPUs are not affected by ITS.
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Mitigation
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----------
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As only the indirect branches and RETs that have their last byte of instruction
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in the lower half of the cacheline are vulnerable to ITS, the basic idea behind
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the mitigation is to not allow indirect branches in the lower half.
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This is achieved by relying on existing retpoline support in the kernel, and in
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compilers. ITS-vulnerable retpoline sites are runtime patched to point to newly
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added ITS-safe thunks. These safe thunks consists of indirect branch in the
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second half of the cacheline. Not all retpoline sites are patched to thunks, if
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a retpoline site is evaluated to be ITS-safe, it is replaced with an inline
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indirect branch.
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Dynamic thunks
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~~~~~~~~~~~~~~
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From a dynamically allocated pool of safe-thunks, each vulnerable site is
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replaced with a new thunk, such that they get a unique address. This could
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improve the branch prediction accuracy. Also, it is a defense-in-depth measure
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against aliasing.
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Note, for simplicity, indirect branches in eBPF programs are always replaced
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with a jump to a static thunk in __x86_indirect_its_thunk_array. If required,
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in future this can be changed to use dynamic thunks.
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All vulnerable RETs are replaced with a static thunk, they do not use dynamic
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thunks. This is because RETs get their prediction from RSB mostly that does not
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depend on source address. RETs that underflow RSB may benefit from dynamic
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thunks. But, RETs significantly outnumber indirect branches, and any benefit
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from a unique source address could be outweighed by the increased icache
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footprint and iTLB pressure.
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Retpoline
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~~~~~~~~~
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Retpoline sequence also mitigates ITS-unsafe indirect branches. For this
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reason, when retpoline is enabled, ITS mitigation only relocates the RETs to
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safe thunks. Unless user requested the RSB-stuffing mitigation.
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RSB Stuffing
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~~~~~~~~~~~~
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RSB-stuffing via Call Depth Tracking is a mitigation for Retbleed RSB-underflow
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attacks. And it also mitigates RETs that are vulnerable to ITS.
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Mitigation in guests
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^^^^^^^^^^^^^^^^^^^^
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All guests deploy ITS mitigation by default, irrespective of eIBRS enumeration
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and Family/Model of the guest. This is because eIBRS feature could be hidden
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from a guest. One exception to this is when a guest enumerates BHI_DIS_S, which
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indicates that the guest is running on an unaffected host.
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To prevent guests from unnecessarily deploying the mitigation on unaffected
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platforms, Intel has defined ITS_NO bit(62) in MSR IA32_ARCH_CAPABILITIES. When
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a guest sees this bit set, it should not enumerate the ITS bug. Note, this bit
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is not set by any hardware, but is **intended for VMMs to synthesize** it for
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guests as per the host's affected status.
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Mitigation options
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^^^^^^^^^^^^^^^^^^
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The ITS mitigation can be controlled using the "indirect_target_selection"
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kernel parameter. The available options are:
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======== ===================================================================
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on (default) Deploy the "Aligned branch/return thunks" mitigation.
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If spectre_v2 mitigation enables retpoline, aligned-thunks are only
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deployed for the affected RET instructions. Retpoline mitigates
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indirect branches.
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off Disable ITS mitigation.
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vmexit Equivalent to "=on" if the CPU is affected by guest/host isolation
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part of ITS. Otherwise, mitigation is not deployed. This option is
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useful when host userspace is not in the threat model, and only
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attacks from guest to host are considered.
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stuff Deploy RSB-fill mitigation when retpoline is also deployed.
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Otherwise, deploy the default mitigation. When retpoline mitigation
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is enabled, RSB-stuffing via Call-Depth-Tracking also mitigates
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ITS.
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force Force the ITS bug and deploy the default mitigation.
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======== ===================================================================
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Sysfs reporting
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---------------
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The sysfs file showing ITS mitigation status is:
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/sys/devices/system/cpu/vulnerabilities/indirect_target_selection
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Note, microcode mitigation status is not reported in this file.
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The possible values in this file are:
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.. list-table::
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* - Not affected
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- The processor is not vulnerable.
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* - Vulnerable
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- System is vulnerable and no mitigation has been applied.
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* - Vulnerable, KVM: Not affected
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- System is vulnerable to intra-mode BTI, but not affected by eIBRS
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guest/host isolation.
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* - Mitigation: Aligned branch/return thunks
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- The mitigation is enabled, affected indirect branches and RETs are
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relocated to safe thunks.
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* - Mitigation: Retpolines, Stuffing RSB
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- The mitigation is enabled using retpoline and RSB stuffing.
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References
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----------
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.. [#f1] Microcode repository - https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
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.. [#f2] Affected Processors list - https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html
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.. [#f3] Affected Processors list (machine readable) - https://github.com/intel/Intel-affected-processor-list

‎Documentation/admin-guide/kernel-parameters.txt‎

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different crypto accelerators. This option can be used
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to achieve best performance for particular HW.
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indirect_target_selection= [X86,Intel] Mitigation control for Indirect
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Target Selection(ITS) bug in Intel CPUs. Updated
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microcode is also required for a fix in IBPB.
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on: Enable mitigation (default).
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off: Disable mitigation.
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force: Force the ITS bug and deploy default
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mitigation.
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vmexit: Only deploy mitigation if CPU is affected by
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guest/host isolation part of ITS.
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stuff: Deploy RSB-fill mitigation when retpoline is
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also deployed. Otherwise, deploy the default
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mitigation.
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For details see:
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Documentation/admin-guide/hw-vuln/indirect-target-selection.rst
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init= [KNL]
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Format: <full_path>
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Run specified binary instead of /sbin/init as init
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expose users to several CPU vulnerabilities.
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Equivalent to: if nokaslr then kpti=0 [ARM64]
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gather_data_sampling=off [X86]
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indirect_target_selection=off [X86]
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kvm.nx_huge_pages=off [X86]
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l1tf=off [X86]
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mds=off [X86]

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