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Merge pull request #1387 from slaclab/fix-axi-resize
Fix AxiResize upsize bug
2 parents 3fba58b + 877a24b commit 26d7e01

2 files changed

Lines changed: 35 additions & 21 deletions

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axi/axi4/rtl/AxiResize.vhd

Lines changed: 34 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ architecture rtl of AxiResize is
6060

6161
type RegType is record
6262
rdCount : slv(BIT_CNT_C-1 downto 0);
63+
rdHold : AxiReadSlaveType;
6364
rdMaster : AxiReadMasterType;
6465
rdSlave : AxiReadSlaveType;
6566
wrCount : slv(BIT_CNT_C-1 downto 0);
@@ -69,6 +70,7 @@ architecture rtl of AxiResize is
6970

7071
constant REG_INIT_C : RegType := (
7172
rdCount => (others => '0'),
73+
rdHold => AXI_READ_SLAVE_INIT_C,
7274
rdMaster => axiReadMasterInit(MASTER_AXI_CONFIG_G),
7375
rdSlave => AXI_READ_SLAVE_INIT_C,
7476
wrCount => (others => '0'),
@@ -162,27 +164,46 @@ begin
162164

163165
v.rdSlave := AXI_READ_SLAVE_INIT_C;
164166

165-
v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := ibRdM.rdata((SLV_BYTES_C*8*rdIdx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*rdIdx));
166-
167-
v.rdSlave.rid := ibRdM.rid;
168-
v.rdSlave.rresp := ibRdM.rresp;
167+
-- Buffer the accepted wide master beat so later narrow slave
168+
-- slices do not depend on the live master-side bus after the
169+
-- current handshake completes.
170+
if (r.rdHold.rvalid = '0') then
171+
v.rdMaster.rready := '1';
172+
173+
if (ibRdM.rvalid = '1') then
174+
v.rdHold := AXI_READ_SLAVE_INIT_C;
175+
v.rdHold.rdata((MST_BYTES_C*8)-1 downto 0) := ibRdM.rdata((MST_BYTES_C*8)-1 downto 0);
176+
v.rdHold.rid := ibRdM.rid;
177+
v.rdHold.rresp := ibRdM.rresp;
178+
v.rdHold.rlast := ibRdM.rlast;
179+
v.rdHold.rvalid := '1';
180+
181+
-- Queue slice 0 immediately while retaining the full
182+
-- beat so the remaining narrow slices can drain from
183+
-- rdHold without an extra bubble.
184+
v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := ibRdM.rdata((SLV_BYTES_C*8)-1 downto 0);
185+
v.rdSlave.rid := ibRdM.rid;
186+
v.rdSlave.rresp := ibRdM.rresp;
187+
v.rdSlave.rvalid := '1';
188+
v.rdSlave.rlast := '0';
189+
v.rdCount := toSlv(1, v.rdCount'length);
190+
end if;
191+
else
192+
v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := r.rdHold.rdata((SLV_BYTES_C*8*rdIdx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*rdIdx));
193+
v.rdSlave.rid := r.rdHold.rid;
194+
v.rdSlave.rresp := r.rdHold.rresp;
195+
v.rdSlave.rvalid := '1';
169196

170-
-- Determine if we move data
171-
if (ibRdM.rvalid = '1') then
172-
if (r.rdCount = (COUNT_C-1)) or ((rdBytes >= rdByteCnt) and (ibRdM.rlast = '1')) then
197+
if (r.rdCount = (COUNT_C-1)) then
173198
v.rdCount := (others => '0');
174-
v.rdMaster.rready := '1';
175-
v.rdSlave.rlast := ibRdM.rlast;
199+
v.rdHold.rvalid := '0';
200+
v.rdSlave.rlast := r.rdHold.rlast;
176201
else
177202
v.rdCount := r.rdCount + 1;
178-
v.rdMaster.rready := '0';
179203
v.rdSlave.rlast := '0';
180204
end if;
181205
end if;
182206

183-
-- Drop transfers, except on tLast
184-
v.rdSlave.rvalid := ibRdM.rvalid or v.rdSlave.rlast;
185-
186207
end if;
187208
end if;
188209

tests/axi/axi4/test_AxiResize.py

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -128,14 +128,7 @@ async def write_read_round_trip_test(dut):
128128

129129
PARAMETER_SWEEP = [
130130
parameter_case("equal_width", SLAVE_DATA_BYTES_G="4", MASTER_DATA_BYTES_G="4"),
131-
pytest.param(
132-
{"SLAVE_DATA_BYTES_G": "4", "MASTER_DATA_BYTES_G": "8"},
133-
id="upsize",
134-
marks=pytest.mark.xfail(
135-
reason="Known RTL bug: 32-bit to 64-bit resize still fails",
136-
strict=False,
137-
),
138-
),
131+
parameter_case("upsize", SLAVE_DATA_BYTES_G="4", MASTER_DATA_BYTES_G="8"),
139132
parameter_case("downsize", SLAVE_DATA_BYTES_G="8", MASTER_DATA_BYTES_G="4"),
140133
]
141134

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