|
| 1 | +/* |
| 2 | + * Copyright (C) 2014-2019 Daniel Rossier <daniel.rossier@heig-vd.ch> |
| 3 | + * |
| 4 | + * This program is free software; you can redistribute it and/or modify |
| 5 | + * it under the terms of the GNU General Public License version 2 as |
| 6 | + * published by the Free Software Foundation. |
| 7 | + * |
| 8 | + * This program is distributed in the hope that it will be useful, |
| 9 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | + * GNU General Public License for more details. |
| 12 | + * |
| 13 | + * You should have received a copy of the GNU General Public License |
| 14 | + * along with this program; if not, write to the Free Software |
| 15 | + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 16 | + * |
| 17 | + */ |
| 18 | + |
| 19 | +/dts-v1/; |
| 20 | + |
| 21 | +/ { |
| 22 | + model = "SO3 RPi4 64-bit capsule machine"; |
| 23 | + compatible = "arm,virt64"; |
| 24 | + |
| 25 | + #address-cells = <2>; |
| 26 | + #size-cells = <2>; |
| 27 | + |
| 28 | + cpus { |
| 29 | + device_type = "cpu"; |
| 30 | + compatible = "arm,virt64"; |
| 31 | + }; |
| 32 | + |
| 33 | + memory { |
| 34 | + device_type = "memory"; |
| 35 | + reg = <0x0 0x41000000 0x0 0x4000000>; /* 64 MB */ |
| 36 | + }; |
| 37 | + |
| 38 | + mem { |
| 39 | + compatible = "mem"; |
| 40 | + status = "ok"; |
| 41 | + }; |
| 42 | + |
| 43 | + soo-serial { |
| 44 | + compatible = "soo-serial"; |
| 45 | + status = "ok"; |
| 46 | + }; |
| 47 | + |
| 48 | + /* SO3 virtual timer managed by AVZ */ |
| 49 | + |
| 50 | + soo-timer { |
| 51 | + compatible = "soo-timer,periodic-timer"; |
| 52 | + status = "ok"; |
| 53 | + }; |
| 54 | + |
| 55 | + /* Free-running clocksource */ |
| 56 | + clocksource-timer { |
| 57 | + compatible = "soo-timer,clocksource-timer"; |
| 58 | + status = "ok"; |
| 59 | + }; |
| 60 | + |
| 61 | + oneshot-timer { |
| 62 | + compatible = "soo-timer,oneshot-timer"; |
| 63 | + status = "ok"; |
| 64 | + }; |
| 65 | + |
| 66 | + /* |
| 67 | + * GIC interrupt controller - BCM2711 GIC-400 addresses. |
| 68 | + * GICD at 0xFF841000: stage-2 fault -> AVZ MMIO emulation. |
| 69 | + * GICC at 0xFF842000: stage-2 mapped to GICV at 0xFF846000. |
| 70 | + */ |
| 71 | + gic: interrupt-controller@0xff841000 { |
| 72 | + compatible = "intc,gic"; |
| 73 | + interrupt-controller; |
| 74 | + #interrupt-cells = <3>; |
| 75 | + |
| 76 | + /* GIC dist, cpu */ |
| 77 | + reg = <0x0 0xff841000 0x0 0x1000 |
| 78 | + 0x0 0xff842000 0x0 0x2000>; |
| 79 | + |
| 80 | + status = "ok"; |
| 81 | + }; |
| 82 | + |
| 83 | + mydev { |
| 84 | + compatible = "arm,mydev"; |
| 85 | + status = "ok"; |
| 86 | + }; |
| 87 | + |
| 88 | + ME { |
| 89 | + /* SPID on 64-bit encoding */ |
| 90 | + spid = /bits/ 64 <0x0030000000000003>; |
| 91 | + |
| 92 | + /* Name of this ME */ |
| 93 | + me_name = "SOO.refso3"; |
| 94 | + |
| 95 | + /* Short description */ |
| 96 | + me_shortdesc = |
| 97 | + |
| 98 | + "This is the standard reference ME that can be used as template or simply to \n \ |
| 99 | + perform various tests. This variant includes a rootfs with some user space \n \ |
| 100 | + applications."; |
| 101 | + |
| 102 | + frontends { |
| 103 | + |
| 104 | + /* Enabling vdummy for testing purposes */ |
| 105 | + vdummy { |
| 106 | + compatible = "vdummy,frontend"; |
| 107 | + status = "disabled"; |
| 108 | + }; |
| 109 | + |
| 110 | + /* Enabling the console */ |
| 111 | + vuart { |
| 112 | + compatible = "vuart,frontend"; |
| 113 | + status = "ok"; |
| 114 | + }; |
| 115 | + |
| 116 | + /* Enabling vlogs - logging supports */ |
| 117 | + vlogs { |
| 118 | + compatible = "vlogs,frontend"; |
| 119 | + status = "ok"; |
| 120 | + }; |
| 121 | + }; |
| 122 | + }; |
| 123 | + |
| 124 | + |
| 125 | +}; |
0 commit comments