From 312329f8dd19be9f25c78aeaa933db03ecb6ee6e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 May 2026 15:08:29 +0200 Subject: [PATCH 1/2] system(g0) update STM32G0xx HAL Drivers to v1.4.7 Included in STM32CubeG0 FW v1.6.3 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 577 +++++++++++++++++- .../Inc/stm32g0xx_hal_adc.h | 35 +- .../Inc/stm32g0xx_hal_comp.h | 62 +- .../Inc/stm32g0xx_hal_crc.h | 4 +- .../Inc/stm32g0xx_hal_cryp_ex.h | 6 +- .../Inc/stm32g0xx_hal_dac.h | 13 +- .../Inc/stm32g0xx_hal_dma_ex.h | 4 +- .../Inc/stm32g0xx_hal_exti.h | 14 +- .../Inc/stm32g0xx_hal_fdcan.h | 4 +- .../Inc/stm32g0xx_hal_flash.h | 11 +- .../Inc/stm32g0xx_hal_gpio.h | 4 +- .../Inc/stm32g0xx_hal_hcd.h | 16 +- .../Inc/stm32g0xx_hal_i2s.h | 4 +- .../Inc/stm32g0xx_hal_lptim.h | 4 +- .../Inc/stm32g0xx_hal_pcd.h | 11 +- .../Inc/stm32g0xx_hal_pcd_ex.h | 1 - .../Inc/stm32g0xx_hal_pwr.h | 2 +- .../Inc/stm32g0xx_hal_pwr_ex.h | 59 +- .../Inc/stm32g0xx_hal_rcc.h | 12 +- .../Inc/stm32g0xx_hal_rcc_ex.h | 4 +- .../Inc/stm32g0xx_hal_rtc.h | 10 +- .../Inc/stm32g0xx_hal_smartcard.h | 6 +- .../Inc/stm32g0xx_hal_spi.h | 52 +- .../Inc/stm32g0xx_hal_tim.h | 43 +- .../Inc/stm32g0xx_hal_uart.h | 13 +- .../Inc/stm32g0xx_hal_usart.h | 15 +- .../Inc/stm32g0xx_ll_adc.h | 16 +- .../Inc/stm32g0xx_ll_comp.h | 14 +- .../Inc/stm32g0xx_ll_crs.h | 19 +- .../Inc/stm32g0xx_ll_dma.h | 8 + .../Inc/stm32g0xx_ll_dmamux.h | 12 +- .../Inc/stm32g0xx_ll_gpio.h | 26 +- .../Inc/stm32g0xx_ll_iwdg.h | 14 +- .../Inc/stm32g0xx_ll_lpuart.h | 19 + .../Inc/stm32g0xx_ll_pwr.h | 131 +++- .../Inc/stm32g0xx_ll_rcc.h | 4 +- .../Inc/stm32g0xx_ll_rng.h | 2 +- .../Inc/stm32g0xx_ll_rtc.h | 208 +++---- .../Inc/stm32g0xx_ll_spi.h | 169 ++--- .../Inc/stm32g0xx_ll_tim.h | 2 +- .../Inc/stm32g0xx_ll_ucpd.h | 59 +- .../Inc/stm32g0xx_ll_usart.h | 4 + .../Inc/stm32g0xx_ll_usb.h | 52 +- system/Drivers/STM32G0xx_HAL_Driver/README.md | 2 +- .../STM32G0xx_HAL_Driver/Release_Notes.html | 223 +++++-- .../STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c | 14 +- .../Src/stm32g0xx_hal_adc_ex.c | 13 +- .../Src/stm32g0xx_hal_comp.c | 8 +- .../Src/stm32g0xx_hal_crc.c | 30 +- .../Src/stm32g0xx_hal_crc_ex.c | 2 - .../Src/stm32g0xx_hal_cryp.c | 90 +-- .../Src/stm32g0xx_hal_cryp_ex.c | 6 +- .../Src/stm32g0xx_hal_dac.c | 5 +- .../Src/stm32g0xx_hal_dac_ex.c | 15 +- .../Src/stm32g0xx_hal_dma.c | 77 ++- .../Src/stm32g0xx_hal_dma_ex.c | 4 +- .../Src/stm32g0xx_hal_exti.c | 18 +- .../Src/stm32g0xx_hal_fdcan.c | 44 +- .../Src/stm32g0xx_hal_flash_ex.c | 2 +- .../Src/stm32g0xx_hal_gpio.c | 16 +- .../Src/stm32g0xx_hal_hcd.c | 303 ++++----- .../Src/stm32g0xx_hal_i2c.c | 103 ++-- .../Src/stm32g0xx_hal_i2s.c | 82 ++- .../Src/stm32g0xx_hal_pcd.c | 177 ++---- .../Src/stm32g0xx_hal_pcd_ex.c | 27 +- .../Src/stm32g0xx_hal_pwr_ex.c | 56 +- .../Src/stm32g0xx_hal_rcc.c | 4 +- .../Src/stm32g0xx_hal_rcc_ex.c | 6 +- .../Src/stm32g0xx_hal_rtc.c | 16 +- .../Src/stm32g0xx_hal_rtc_ex.c | 14 +- .../Src/stm32g0xx_hal_smartcard.c | 2 +- .../Src/stm32g0xx_hal_smbus.c | 55 +- .../Src/stm32g0xx_hal_smbus_ex.c | 2 + .../Src/stm32g0xx_hal_spi.c | 520 ++++++++-------- .../Src/stm32g0xx_hal_tim.c | 101 ++- .../Src/stm32g0xx_hal_tim_ex.c | 12 +- ...tm32g0xx_hal_timebase_rtc_alarm_template.c | 2 +- ...m32g0xx_hal_timebase_rtc_wakeup_template.c | 2 +- .../Src/stm32g0xx_hal_timebase_tim_template.c | 14 + .../Src/stm32g0xx_hal_uart.c | 217 ++++--- .../Src/stm32g0xx_hal_uart_ex.c | 54 +- .../Src/stm32g0xx_hal_usart.c | 17 +- .../Src/stm32g0xx_hal_usart_ex.c | 2 +- .../Src/stm32g0xx_ll_adc.c | 2 +- .../Src/stm32g0xx_ll_comp.c | 6 +- .../Src/stm32g0xx_ll_crs.c | 6 +- .../Src/stm32g0xx_ll_gpio.c | 2 +- .../Src/stm32g0xx_ll_rcc.c | 2 +- .../Src/stm32g0xx_ll_rng.c | 2 +- .../Src/stm32g0xx_ll_spi.c | 11 +- .../Src/stm32g0xx_ll_tim.c | 2 - .../Src/stm32g0xx_ll_ucpd.c | 2 +- .../Src/stm32g0xx_ll_usb.c | 233 ++++--- .../Src/stm32g0xx_ll_utils.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 95 files changed, 2699 insertions(+), 1677 deletions(-) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 3caddb5298..58261ea60e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -103,7 +103,15 @@ extern "C" { #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ - +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -207,6 +215,9 @@ extern "C" { #endif +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif /** * @} @@ -216,6 +227,11 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ /** * @} */ @@ -223,10 +239,13 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ +#if defined(STM32H5) || defined(STM32C0) +#else #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif /** * @} */ @@ -256,12 +275,22 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ defined(STM32F4) || defined(STM32G4) @@ -332,7 +361,9 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -408,6 +439,9 @@ extern "C" { #endif /* STM32H7 */ +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -440,7 +474,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -487,7 +523,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -504,6 +540,35 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -547,6 +612,113 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ /** @@ -624,12 +796,13 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -646,6 +819,28 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -653,6 +848,27 @@ extern "C" { /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -679,6 +895,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -816,8 +1036,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -900,6 +1120,11 @@ extern "C" { * @} */ +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ /** * @} */ @@ -967,7 +1192,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1063,25 +1288,42 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - - - -#if defined(STM32F7) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1248,6 +1490,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1398,7 +1644,7 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ -#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ /** * @} @@ -1448,7 +1694,9 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -1458,7 +1706,7 @@ extern "C" { * @} */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1482,6 +1730,10 @@ extern "C" { * @{ */ +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ /** * @} @@ -1604,7 +1856,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1665,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -1692,6 +1948,95 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -1700,6 +2045,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -1807,6 +2158,13 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + /** * @} */ @@ -2014,8 +2372,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2048,8 +2406,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2106,8 +2464,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2124,7 +2482,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2426,6 +2784,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3349,8 +3713,11 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3452,8 +3819,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3462,7 +3831,124 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ /** * @} @@ -3480,7 +3966,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3540,6 +4026,10 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ /** * @} @@ -3770,6 +4260,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h index 190e55f81b..6455684242 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h @@ -811,11 +811,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -/** * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed * to result as the ADC oversampling conversion data (before potential shift) + * @{ */ #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ @@ -830,21 +828,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift - * @{ - */ -/** * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling - * conversion data) + * conversion data + * @{ */ #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 rank */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 rank */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 rank */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 rank */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 rank */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 rank */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 rank */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 rank */ /** * @} */ @@ -861,14 +857,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode - * @{ - */ - -/** * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion * start trigger event). * Duration value: Refer to device datasheet, parameter "tIdle". + * @{ */ #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ @@ -877,11 +870,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_Event_type ADC Event type - * @{ - */ -/** * @note Analog watchdog 1 is available on all stm32 series * Analog watchdog 2 and 3 are not available on all series + * @{ */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h index 12831e360e..a3479956f0 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h @@ -440,16 +440,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ } while(0) @@ -536,17 +536,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ } while(0) @@ -632,19 +632,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP3 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) +#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) +#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);\ + } while(0) /** * @brief Enable the COMP3 EXTI line in interrupt mode. @@ -808,14 +808,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)) #define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ @@ -827,12 +827,12 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__POL__) == COMP_OUTPUTPOL_INVERTED)) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \ ) /* Note: Output blanking source common to all COMP instances */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h index 0a4ddcc3c3..b8c4494946 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc.h @@ -308,8 +308,8 @@ void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions * @{ */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h index d87d7c5ee5..40d68735bd 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h @@ -93,8 +93,10 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h index 5059aeb8b1..a868fb6566 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h @@ -271,9 +271,16 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_DISABLE (0x00000000UL) -#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) - +#define DAC_CHIPCONNECT_DISABLE (0x00000000UL) /*!< DAC channel output is connected to external + pin. + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to on-chip + peripherals, refer to ref manual. */ +#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) /*!< DAC channel output is connected to on-chip + peripherals (via internal paths). + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to external pin, + refer to ref manual. */ /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h index b48dec7721..8cc69f75c7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h @@ -204,13 +204,13 @@ typedef struct /* ------------------------- REQUEST -----------------------------------------*/ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, - HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); + const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); /* -------------------------------------------------------------------------- */ /* ------------------------- SYNCHRO -----------------------------------------*/ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma,const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); /* -------------------------------------------------------------------------- */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h index 69ad3553de..7c5f31490c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h @@ -344,9 +344,9 @@ typedef struct * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** @@ -358,10 +358,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @{ */ /* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h index ae852b6099..79ad97896e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h index 25a316affe..5e3f103147 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h @@ -197,9 +197,6 @@ typedef struct #endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /*!< FLASH Operation Busy flag - legacy name for single bank */ #define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos) /*!< FLASH Configuration Busy flag */ -#if defined(FLASH_DBANK_SUPPORT) -#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos) /*!< FLASH Programming/erase operation suspended */ -#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos) /*!< FLASH ECC correction on bank 1 */ #define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos) /*!< FLASH ECC detection on bank 1 */ #if defined(FLASH_DBANK_SUPPORT) @@ -557,8 +554,8 @@ typedef struct /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit * @{ */ -#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ -#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ +#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset handler disable */ /** * @} */ @@ -905,11 +902,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); FLASH_SR_OPTVERR) /*!< All SR error flags */ #endif /* FLASH_PCROP_SUPPORT */ -#if defined(FLASH_DBANK_SUPPORT) -#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD) -#else #define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP) -#endif /* FLASH_DBANK_SUPPORT */ /* Internal defines for HAL macro usage */ #define FLASH_FLAG_REG_POS 16u diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h index 3768993214..07315897d9 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h @@ -317,7 +317,7 @@ typedef enum */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** @@ -330,7 +330,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h index a6dd469e6b..bdf0b7691f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_hcd.h @@ -126,6 +126,9 @@ typedef struct /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ /** @defgroup HCD_Speed HCD Speed * @{ @@ -151,6 +154,8 @@ typedef struct */ #define HCD_PHY_ULPI 1U #define HCD_PHY_EMBEDDED 2U +#define HCD_HS_PHY_EMBEDDED 3U +#define HCD_PHY_UTMI 3U /** * @} */ @@ -205,6 +210,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); @@ -359,12 +365,15 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind * @{ */ -#define HCD_SNG_BUF 0U -#define HCD_DBL_BUF 1U +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U /** * @} */ +/* Powerdown exit count */ +#define HCD_PDWN_EXIT_CNT 0x100U + /* Set Channel */ #define HCD_SET_CHANNEL USB_DRD_SET_CHEP @@ -495,13 +504,14 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) { uint32_t HostCoreSpeed; + uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum); __IO uint32_t count = 10U; /* Get Host core Speed */ HostCoreSpeed = USB_GetHostSpeed(Instance); /* Count depends on device LS */ - if (HostCoreSpeed == USB_DRD_SPEED_LS) + if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) { count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h index d98518f796..946fdfa398 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h @@ -452,8 +452,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h index 0a00928b01..6693b5d2e6 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_lptim.h @@ -696,9 +696,9 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h index 78543fd34f..10b7a1c653 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd.h @@ -159,6 +159,7 @@ typedef struct */ #define PCD_PHY_ULPI 1U #define PCD_PHY_EMBEDDED 2U +#define PCD_HS_PHY_EMBEDDED 3U #define PCD_PHY_UTMI 3U /** * @} @@ -361,7 +362,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 4) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1UL << 4) /*!< USB FS EXTI Line WakeUp Interrupt */ /** @@ -462,6 +463,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd_ex.h index 4e3ca49ef0..5ac83be6e6 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h index 2defd85032..e8e5543991 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h @@ -157,7 +157,7 @@ extern "C" { #define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO) /*!< Power Voltage Detector output */ #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) -#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB) /*!< Power Voltage Monitoring output */ +#define PWR_FLAG_PVMO_VDDIO2 (0x00020000u | PWR_SR2_PVMO_VDDIO2) /*!< Power Voltage Monitoring output */ #endif /* PWR_PVM_SUPPORT */ /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h index 7a334980ce..b017290209 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h @@ -47,9 +47,8 @@ extern "C" { */ typedef struct { - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */ + uint32_t PVMType; /*!< PVMType: Specifies the VDDIO2 Power Voltage Monitoring type. + This parameter can be a value of @ref PWREx_PVM_Type. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVM_Mode. */ @@ -141,10 +140,13 @@ typedef struct #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) -/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type +/** @defgroup PWREx_PVM_Type VDDIO2 Power Voltage Monitoring type * @{ */ -#define PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */ +#define PWR_PVM_DISABLE ((uint32_t)0x00000000) /*!< VDDIO2 monitoring disabled, IOs in isolation mode */ +#define PWR_PVM_ENABLE ((uint32_t)PWR_CR2_PVM_VDDIO2_0) /*!< VDDIO2 monitoring enabled, IOs enabled or in isolation mode, according to VDDIO2 level */ +#define PWR_PVM_BYPASS ((uint32_t)(PWR_CR2_PVM_VDDIO2_1 | PWR_CR2_PVM_VDDIO2_2)) /*!< VDDIO2 monitoring bypassed, IOs enabled */ + /** * @} */ @@ -256,7 +258,7 @@ typedef struct * @{ */ #if defined(PWR_PVM_SUPPORT) -#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */ +#define PWR_FLAG_PVMOVDDIO2 (0x00020000u | PWR_SR2_PVMO_VDDIO2) /*!< VDDIO2 supply voltage monitoring output flag */ #endif /* PWR_PVM_SUPPORT */ /** * @} @@ -468,6 +470,16 @@ typedef struct * @retval None */ #define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Get Power Voltage Monitoring Type + * @retval Returned value can be one of the following values: + * @arg @ref PWR_PVM_ENABLE + * @arg @ref PWR_PVM_BYPASS + * @arg @ref PWR_PVM_DISABLE + */ +#define __HAL_PWR_PVM_GET_PVM_TYPE() READ_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2) + #endif /* PWR_PVM_SUPPORT */ /** * @} @@ -536,14 +548,16 @@ typedef struct #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) -#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB) - -#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ +#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_DISABLE) || \ + ((TYPE) == PWR_PVM_ENABLE) || \ + ((TYPE) == PWR_PVM_BYPASS)) + +#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) || \ + ((MODE) == PWR_PVM_MODE_IT_RISING) || \ + ((MODE) == PWR_PVM_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) || \ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) || \ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) #endif /* PWR_PVM_SUPPORT */ /** @@ -584,17 +598,13 @@ uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); #if defined(PWR_PVD_SUPPORT) /* Power voltage detection configuration functions ****************************/ -HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD); void HAL_PWREx_EnablePVD(void); void HAL_PWREx_DisablePVD(void); #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) -/* Power voltage monitoring configuration functions ***************************/ -void HAL_PWREx_EnableVddIO2(void); -void HAL_PWREx_DisableVddIO2(void); -void HAL_PWREx_EnablePVMUSB(void); -void HAL_PWREx_DisablePVMUSB(void); -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +/* Power voltage monitoring configuration function ****************************/ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM); #endif /* PWR_PVM_SUPPORT */ #if defined(PWR_CR2_USV) void HAL_PWREx_EnableVddUSB(void); @@ -616,6 +626,13 @@ void HAL_PWREx_PVD_IRQHandler(void); void HAL_PWREx_PVD_Rising_Callback(void); void HAL_PWREx_PVD_Falling_Callback(void); #endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */ +#if defined(PWR_PVM_SUPPORT) +/* Deprecated functions: retained only to ensure backward compatibility */ +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +void HAL_PWREx_EnablePVMUSB(void); +void HAL_PWREx_DisablePVMUSB(void); +#endif /* PWR_PVM_SUPPORT */ /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h index dce1f7bbb4..cc4a6ce8ee 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h @@ -652,10 +652,10 @@ typedef struct #define RCC_MCO_INDEX_POS 28U #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ -#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) -#define RCC_MCO_PA9 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) -#define RCC_MCO_PD10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Not defined for all stm32g0xx family lines */ -#define RCC_MCO_PF2 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) /* Not defined for all stm32g0xx family lines */ +#define RCC_MCO_PA8 (RCC_MCO1_INDEX | ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | ((uint32_t)GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO_PA9 (RCC_MCO1_INDEX | ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | ((uint32_t)GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) +#define RCC_MCO_PD10 (RCC_MCO1_INDEX | ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | ((uint32_t)GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Not defined for all stm32g0xx family lines */ +#define RCC_MCO_PF2 (RCC_MCO1_INDEX | ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | ((uint32_t)GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) /* Not defined for all stm32g0xx family lines */ #define RCC_MCO1 RCC_MCO_PA8 #if defined(RCC_MCO2_SUPPORT) @@ -3117,8 +3117,8 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h index 9c2cddabed..8e61d6d25f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h @@ -1190,7 +1190,7 @@ typedef struct * @{ */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); @@ -1215,7 +1215,7 @@ void HAL_RCCEx_DisableLSCO(void); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h index 6fbda727fd..28f7f2ebd1 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h @@ -770,14 +770,14 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc); /** * @} */ @@ -789,7 +789,7 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); @@ -810,7 +810,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h index 7e7ff5813f..9c74413992 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h @@ -721,13 +721,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h index 4416e93a3c..adeeb0d3d4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -754,6 +758,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) +/** @brief Checks if a data address is 16bit aligned. + * @param __DATA__ specifies a data address. + * @retval None + */ +#define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U) + /** * @} */ @@ -789,17 +799,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +835,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h index 44e276db26..b7c120f4fe 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h @@ -1764,7 +1764,8 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} @@ -2145,20 +2146,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2172,16 +2168,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h index e8f3c25ef7..21a18847dd 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -1229,7 +1227,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1244,8 +1242,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h index f73166a390..8583852226 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart.h @@ -545,10 +545,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -570,10 +570,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -703,8 +703,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h index 7db42c89fc..97654e1c12 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h @@ -63,7 +63,6 @@ extern "C" { #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ - /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ @@ -93,7 +92,6 @@ extern "C" { #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ - /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ @@ -220,7 +218,6 @@ extern "C" { #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) - /* ADC registers bits positions */ #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ @@ -3901,7 +3898,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) - & 0x1FUL)); + & 0x1FUL)) & 0x01UL; /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) @@ -3985,7 +3982,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, * @arg @ref LL_ADC_AWD_CH_VBAT_REG * @retval None */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef const *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) { /* Set bits with content of parameter "AWDChannelGroup" with bits position */ /* in register and register position depending on parameter "AWDy". */ @@ -4205,7 +4202,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef const *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) { /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ @@ -4288,7 +4285,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef const *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ @@ -4777,8 +4774,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *A /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). + * features extending data width (oversampling, data shift,...). * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF @@ -5455,7 +5451,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef const *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h index 8bd0e3b9d5..931c24ffe7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_comp.h @@ -321,13 +321,9 @@ typedef struct #if defined(COMP3) #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ ((((__COMPx__) == COMP3)) \ - ? ( \ - (COMP23_COMMON) \ - ) \ - : \ - ( \ - (COMP12_COMMON) \ - ) \ + ? ((COMP23_COMMON)) \ + : \ + ((COMP12_COMMON)) \ ) #else #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ @@ -347,8 +343,8 @@ typedef struct * @{ */ -/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: - * common to several COMP instances +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration + * of COMP hierarchical scope: common to several COMP instances * @{ */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crs.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crs.h index 9c967139f4..8c8d39cedd 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crs.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crs.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. + * Copyright (c) 2018 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -41,7 +41,6 @@ extern "C" { /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants @@ -135,11 +134,12 @@ extern "C" { /** * @brief Reset value of the HSI48 Calibration field - * @note The default value is 64, which corresponds to the middle of the trimming interval. + * @note The default value is 64, + * which corresponds to the middle of the trimming interval. * The trimming step is specified in the product datasheet. * A higher TRIM value corresponds to a higher output frequency. */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /** * @} */ @@ -441,15 +441,18 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 * @param Settings This parameter can be a combination of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 - * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 + * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 + * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING * @retval None */ -__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, + uint32_t ReloadValue, uint32_t Settings) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h index 57db1bc6c0..935c1dc0bc 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h @@ -1261,6 +1261,10 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMAMUX_REQ_USART3_TX * @arg @ref LL_DMAMUX_REQ_USART4_RX * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_USART5_RX + * @arg @ref LL_DMAMUX_REQ_USART5_TX + * @arg @ref LL_DMAMUX_REQ_USART6_RX + * @arg @ref LL_DMAMUX_REQ_USART6_TX * @arg @ref LL_DMAMUX_REQ_UCPD1_RX * @arg @ref LL_DMAMUX_REQ_UCPD1_TX * @arg @ref LL_DMAMUX_REQ_UCPD2_RX @@ -1346,6 +1350,10 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t C * @arg @ref LL_DMAMUX_REQ_USART3_TX * @arg @ref LL_DMAMUX_REQ_USART4_RX * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_USART5_RX + * @arg @ref LL_DMAMUX_REQ_USART5_TX + * @arg @ref LL_DMAMUX_REQ_USART6_RX + * @arg @ref LL_DMAMUX_REQ_USART6_TX * @arg @ref LL_DMAMUX_REQ_UCPD1_RX * @arg @ref LL_DMAMUX_REQ_UCPD1_TX * @arg @ref LL_DMAMUX_REQ_UCPD2_RX diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h index c8086345cf..578d53261f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h @@ -250,10 +250,8 @@ extern "C" { #define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */ #endif /* USART6 */ -#if defined(STM32G0C1xx)||defined(STM32G0B1xx) +#if defined(STM32G0C1xx)||defined(STM32G0B1xx)||defined(STM32G0B0xx) #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX -#elif defined(STM32G0B0xx) -#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX #elif defined(STM32G081xx)||defined(STM32G071xx) #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_UCPD2_TX #elif defined(STM32G070xx) @@ -515,6 +513,10 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_USART3_TX * @arg @ref LL_DMAMUX_REQ_USART4_RX * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_USART5_RX + * @arg @ref LL_DMAMUX_REQ_USART5_TX + * @arg @ref LL_DMAMUX_REQ_USART6_RX + * @arg @ref LL_DMAMUX_REQ_USART6_TX * @arg @ref LL_DMAMUX_REQ_UCPD1_RX * @arg @ref LL_DMAMUX_REQ_UCPD1_TX * @arg @ref LL_DMAMUX_REQ_UCPD2_RX @@ -607,6 +609,10 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_USART3_TX * @arg @ref LL_DMAMUX_REQ_USART4_RX * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_USART5_RX + * @arg @ref LL_DMAMUX_REQ_USART5_TX + * @arg @ref LL_DMAMUX_REQ_USART6_RX + * @arg @ref LL_DMAMUX_REQ_USART6_TX * @arg @ref LL_DMAMUX_REQ_UCPD1_RX * @arg @ref LL_DMAMUX_REQ_UCPD1_TX * @arg @ref LL_DMAMUX_REQ_UCPD2_RX diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h index 2b221dd9a1..ad58c1787d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h @@ -314,7 +314,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); } @@ -382,7 +382,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); } @@ -455,7 +455,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); } @@ -520,7 +520,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); } @@ -580,7 +580,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); @@ -642,7 +642,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef const *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * @@ -714,7 +714,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef const *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -725,7 +725,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef const *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -744,7 +744,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef const *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -773,7 +773,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef const *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -796,7 +796,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef const *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -825,7 +825,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef const *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -928,7 +928,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef const *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h index ae5604daff..38ba8afe5f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef const *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef const *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef const *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef const *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef const *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef const *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef const *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h index 1450dda58a..1839e2e264 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** @@ -2605,6 +2609,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h index 07089678f5..a05d8021c5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h @@ -118,7 +118,7 @@ extern "C" { /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL * @{ */ -#define LL_PWR_PVDLLEVEL_0 0x000000000u /* VPVD0 > 2.05 V */ +#define LL_PWR_PVDLLEVEL_0 0x000000000U /* VPVD0 > 2.05 V */ #define LL_PWR_PVDLLEVEL_1 (PWR_CR2_PVDFT_0) /* VPVD0 > 2.2 V */ #define LL_PWR_PVDLLEVEL_2 (PWR_CR2_PVDFT_1) /* VPVD1 > 2.36 V */ #define LL_PWR_PVDLLEVEL_3 (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0) /* VPVD2 > 2.52 V */ @@ -126,7 +126,7 @@ extern "C" { #define LL_PWR_PVDLLEVEL_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /* VPVD4 > 2.81 V */ #define LL_PWR_PVDLLEVEL_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /* VPVD5 > 2.91 V */ -#define LL_PWR_PVDHLEVEL_0 0x00000000u /* VPDD0 > 2.15 V */ +#define LL_PWR_PVDHLEVEL_0 0x00000000U /* VPDD0 > 2.15 V */ #define LL_PWR_PVDHLEVEL_1 (PWR_CR2_PVDRT_0) /* VPVD1 > 2.3 V */ #define LL_PWR_PVDHLEVEL_2 (PWR_CR2_PVDRT_1) /* VPVD1 > 2.46 V */ #define LL_PWR_PVDHLEVEL_3 (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* VPVD2 > 2.62 V */ @@ -143,10 +143,22 @@ extern "C" { /** @defgroup PWR_LL_EC_PVM_IP PVM_IP * @{ */ -#define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */ +#define LL_PWR_PVM_DISABLE 0x00000000U /*!< VDDIO2 monitoring disabled, IOs in isolation mode */ +#define LL_PWR_PVM_ENABLE (PWR_CR2_PVM_VDDIO2_0) /*!< VDDIO2 monitoring enabled, IOs enabled or in isolation mode, according to VDDIO2 level */ +#define LL_PWR_PVM_BYPASS (PWR_CR2_PVM_VDDIO2_1 | PWR_CR2_PVM_VDDIO2_2) /*!< VDDIO2 monitoring bypassed, IOs enabled */ /** * @} */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_PWR_PVM_USB LL_PWR_PVM_ENABLE +#define LL_PWR_IsActiveFlag_PVMOUSB LL_PWR_IsActiveFlag_PVMOVDDIO2 +/** +@endcond + */ + #endif /* PWR_PVM_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP WAKEUP @@ -169,7 +181,7 @@ extern "C" { /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR * @{ */ -#define LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000u +#define LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000U #define LL_PWR_BATTCHARG_RESISTOR_1_5K (PWR_CR4_VBRS) /** * @} @@ -193,22 +205,22 @@ extern "C" { /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT * @{ */ -#define LL_PWR_GPIO_BIT_0 0x00000001u -#define LL_PWR_GPIO_BIT_1 0x00000002u -#define LL_PWR_GPIO_BIT_2 0x00000004u -#define LL_PWR_GPIO_BIT_3 0x00000008u -#define LL_PWR_GPIO_BIT_4 0x00000010u -#define LL_PWR_GPIO_BIT_5 0x00000020u -#define LL_PWR_GPIO_BIT_6 0x00000040u -#define LL_PWR_GPIO_BIT_7 0x00000080u -#define LL_PWR_GPIO_BIT_8 0x00000100u -#define LL_PWR_GPIO_BIT_9 0x00000200u -#define LL_PWR_GPIO_BIT_10 0x00000400u -#define LL_PWR_GPIO_BIT_11 0x00000800u -#define LL_PWR_GPIO_BIT_12 0x00001000u -#define LL_PWR_GPIO_BIT_13 0x00002000u -#define LL_PWR_GPIO_BIT_14 0x00004000u -#define LL_PWR_GPIO_BIT_15 0x00008000u +#define LL_PWR_GPIO_BIT_0 0x00000001U +#define LL_PWR_GPIO_BIT_1 0x00000002U +#define LL_PWR_GPIO_BIT_2 0x00000004U +#define LL_PWR_GPIO_BIT_3 0x00000008U +#define LL_PWR_GPIO_BIT_4 0x00000010U +#define LL_PWR_GPIO_BIT_5 0x00000020U +#define LL_PWR_GPIO_BIT_6 0x00000040U +#define LL_PWR_GPIO_BIT_7 0x00000080U +#define LL_PWR_GPIO_BIT_8 0x00000100U +#define LL_PWR_GPIO_BIT_9 0x00000200U +#define LL_PWR_GPIO_BIT_10 0x00000400U +#define LL_PWR_GPIO_BIT_11 0x00000800U +#define LL_PWR_GPIO_BIT_12 0x00001000U +#define LL_PWR_GPIO_BIT_13 0x00002000U +#define LL_PWR_GPIO_BIT_14 0x00004000U +#define LL_PWR_GPIO_BIT_15 0x00008000U /** * @} */ @@ -456,6 +468,10 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void) /** * @brief Enable VDDIO2 supply * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ __STATIC_INLINE void LL_PWR_EnableVddIO2(void) @@ -466,6 +482,10 @@ __STATIC_INLINE void LL_PWR_EnableVddIO2(void) /** * @brief Disable VDDIO2 supply * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) @@ -476,6 +496,10 @@ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) /** * @brief Check if VDDIO2 supply is enabled * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_GetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) @@ -488,6 +512,10 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) /** * @brief Enable VDDUSB supply * @rmtoll CR2 USV LL_PWR_EnableVddUSB + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ __STATIC_INLINE void LL_PWR_EnableVddUSB(void) @@ -498,6 +526,10 @@ __STATIC_INLINE void LL_PWR_EnableVddUSB(void) /** * @brief Disable VDDUSB supply * @rmtoll CR2 USV LL_PWR_DisableVddUSB + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ __STATIC_INLINE void LL_PWR_DisableVddUSB(void) @@ -508,6 +540,10 @@ __STATIC_INLINE void LL_PWR_DisableVddUSB(void) /** * @brief Check if VDDUSB supply is enabled * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_GetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) @@ -519,9 +555,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) #if defined (PWR_PVM_SUPPORT) /** * @brief Enable the Power Voltage Monitoring on a peripheral - * @rmtoll CR2 PVMUSB LL_PWR_EnablePVM + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". + * @rmtoll CR2 PVMUSB LL_PWR_PVM_USB * @param PeriphVoltage This parameter can be one of the following values: - * @arg @ref LL_PWR_PVM_USB (*) + * @arg @ref LL_PWR_PVM_ENABLE (*) * * (*) value not defined in all devices * @retval None @@ -533,6 +573,10 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) /** * @brief Disable the Power Voltage Monitoring on a peripheral + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_SetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @rmtoll CR2 PVMUSB LL_PWR_DisablePVM * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_USB (*) @@ -547,6 +591,10 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) /** * @brief Check if Power Voltage Monitoring is enabled on a peripheral + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by LL_PWR_GetPVM(). + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @rmtoll CR2 PVMUSB LL_PWR_IsEnabledPVM * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_USB (*) @@ -558,6 +606,34 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) { return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); } + +/** + * @brief Set Power Voltage Monitoring mode + * @rmtoll CR2 PVM_VDDIO2 LL_PWR_SetPVM + * @param PVM_Mode This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_ENABLE + * @arg @ref LL_PWR_PVM_BYPASS + * @arg @ref LL_PWR_PVM_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVM(uint32_t PVM_Mode) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PVM_VDDIO2, PVM_Mode); +} + +/** + * @brief Get Power Voltage Monitoring mode + * @rmtoll CR2 PVM_VDDIO2 LL_PWR_GetPVM + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVM_ENABLE + * @arg @ref LL_PWR_PVM_BYPASS + * @arg @ref LL_PWR_PVM_DISABLE + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVM(void) +{ + return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2)); +} + #endif /* PWR_PVM_SUPPORT */ /** @@ -1421,14 +1497,15 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) #if defined (PWR_PVM_SUPPORT) /** - * @brief Indicate whether VDD voltage is below or above the selected PVD - * threshold - * @rmtoll SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB + * @brief Indicate whether VDDIO2 voltage is below or above the 1.2V threshold + * @rmtoll SR2 PVMO_VDDIO2 LL_PWR_IsActiveFlag_PVMOVDDIO2 + * @note: Take care, return value "0" means VDDIO2 is ready. + Return value "1" VDDIO2 is not ready (below 1.2 V threshold). * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void) +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOVDDIO2(void) { - return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_VDDIO2) == (PWR_SR2_PVMO_VDDIO2)) ? 1UL : 0UL); } #endif /* PWR_PVM_SUPPORT */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h index 135b67097b..b1c5f13002 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h @@ -473,11 +473,11 @@ typedef struct /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection * @{ */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000UL >> 16UL)) /*!< PCLK1 selected as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */ #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */ -#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000UL >> 16UL)) /*!< PCLK1 selected as LPTIM2 clock */ #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */ #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */ #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h index 1cbd5c1436..6eef9a35d0 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rng.h @@ -369,7 +369,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h index 50e812bc94..9fcbd09b15 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rtc.h @@ -743,7 +743,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -775,7 +775,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -802,7 +802,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); } @@ -857,7 +857,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -891,7 +891,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } @@ -952,7 +952,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1021,7 +1021,7 @@ __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL); } @@ -1054,7 +1054,7 @@ __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL); } @@ -1090,7 +1090,7 @@ __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL); } @@ -1131,7 +1131,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1166,7 +1166,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1201,7 +1201,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)))>> RTC_TR_MNU_Pos); } @@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos); } @@ -1290,7 +1290,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef const *RTCx) { uint32_t temp; @@ -1330,7 +1330,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1429,7 +1429,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1468,7 +1468,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1522,7 +1522,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos); } @@ -1552,7 +1552,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1620,7 +1620,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef const *RTCx) { uint32_t temp; @@ -1699,7 +1699,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1749,7 +1749,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -1786,7 +1786,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -1813,7 +1813,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -1841,7 +1841,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -1869,7 +1869,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -1897,7 +1897,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -1969,7 +1969,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2065,7 +2065,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2115,7 +2115,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2152,7 +2152,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2179,7 +2179,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2207,7 +2207,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2263,7 +2263,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2335,7 +2335,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2358,7 +2358,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2444,7 +2444,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2457,7 +2457,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2470,7 +2470,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2483,7 +2483,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2496,7 +2496,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2514,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2533,7 +2533,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2558,7 +2558,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2571,7 +2571,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2588,7 +2588,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2599,7 +2599,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -2792,7 +2792,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Du * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef const *TAMPx) { return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH)); } @@ -2823,7 +2823,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef const *TAMPx) { return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT)); } @@ -2862,7 +2862,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef const *TAMPx) { return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ)); } @@ -2990,7 +2990,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } @@ -3027,7 +3027,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3051,7 +3051,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup * @arg @ref LL_RTC_BKP_DR4 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef const *TAMPx, uint32_t BackupRegister) { const __IO uint32_t *tmp; @@ -3144,7 +3144,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3171,7 +3171,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } @@ -3204,7 +3204,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3229,7 +3229,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3248,7 +3248,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL); } @@ -3259,7 +3259,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL); } @@ -3270,7 +3270,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL); } @@ -3281,7 +3281,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL); } @@ -3292,7 +3292,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL); } @@ -3303,7 +3303,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL); } @@ -3314,7 +3314,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL); } @@ -3391,7 +3391,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL); } @@ -3402,7 +3402,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL); } @@ -3424,7 +3424,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL); } @@ -3435,7 +3435,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL); } @@ -3446,7 +3446,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL); } @@ -3457,7 +3457,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL); } @@ -3468,7 +3468,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL); } @@ -3479,7 +3479,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL); } @@ -3490,7 +3490,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL); } @@ -3501,7 +3501,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL); } @@ -3512,7 +3512,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL); } @@ -3523,7 +3523,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL); } @@ -3534,7 +3534,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL); } @@ -3545,7 +3545,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL); } @@ -3556,7 +3556,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL); } @@ -3579,7 +3579,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1UL : 0UL); } @@ -3590,7 +3590,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1UL : 0UL); } @@ -3601,7 +3601,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1UL : 0UL); } @@ -3612,7 +3612,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1UL : 0UL); } @@ -3624,7 +3624,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL); } @@ -3635,7 +3635,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL); } @@ -3659,7 +3659,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1UL : 0UL); } @@ -3670,7 +3670,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1UL : 0UL); } @@ -3681,7 +3681,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1UL : 0UL); } @@ -3692,7 +3692,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1UL : 0UL); } @@ -3888,7 +3888,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } @@ -3899,7 +3899,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } @@ -3910,7 +3910,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } @@ -3921,7 +3921,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } @@ -4089,7 +4089,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL); } @@ -4100,7 +4100,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL); } @@ -4124,7 +4124,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1UL : 0UL); } @@ -4135,7 +4135,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1UL : 0UL); } @@ -4146,7 +4146,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1UL : 0UL); } @@ -4157,7 +4157,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(TAMP_TypeDef *TAMPx) * @param TAMPx TAMP Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(TAMP_TypeDef *TAMPx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(TAMP_TypeDef const *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_spi.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_spi.h index 9643b57363..ea9a51694d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_spi.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1656,7 +1671,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1689,7 +1704,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1716,7 +1731,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1751,7 +1766,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1782,7 +1797,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1805,7 +1820,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1832,7 +1847,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1865,7 +1880,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1899,7 +1914,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1919,7 +1934,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1930,7 +1945,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1941,7 +1956,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1952,7 +1967,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1963,7 +1978,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1974,7 +1989,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1988,7 +2003,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -2010,7 +2025,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2023,7 +2038,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2110,7 +2125,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2121,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2132,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2173,7 +2188,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2206,7 +2221,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2251,8 +2266,8 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h index ad8d1def4e..13e23af486 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h @@ -150,7 +150,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ #define OCREF_CLEAR_SELECT_Pos (16U) -#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */ +#define OCREF_CLEAR_SELECT_Msk (0x1UL << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */ /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h index 29d5ae2243..efce9cacef 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_ucpd.h @@ -847,7 +847,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1012,7 +1012,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1177,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1350,7 +1350,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1446,10 +1446,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1460,7 +1460,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1471,7 +1471,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1479,10 +1479,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1490,10 +1501,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1512,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1512,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1523,7 +1534,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1833,7 +1844,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h index 09b8d76aac..3f9de2e4b3 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h index 5e77e649dc..0ae273fc47 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h +++ b/system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usb.h @@ -51,6 +51,7 @@ typedef enum USB_HOST_MODE = 1 } USB_ModeTypeDef; +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief URB States definition */ @@ -61,7 +62,8 @@ typedef enum URB_NOTREADY, URB_NYET, URB_ERROR, - URB_STALL + URB_STALL, + URB_NAK_WAIT } USB_URBStateTypeDef; /** @@ -80,6 +82,7 @@ typedef enum HC_BBLERR, HC_DATATGLERR } USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** @@ -122,6 +125,7 @@ typedef struct uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -166,7 +170,9 @@ typedef struct uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ +#if defined (HAL_HCD_MODULE_ENABLED) typedef struct { uint8_t dev_addr; /*!< USB device address. @@ -232,13 +238,20 @@ typedef struct USB_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_DRD_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /* Exported constants --------------------------------------------------------*/ @@ -337,8 +350,8 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; * @} */ /******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 26) -#define USB_CNTRX_BLSIZE (0x1U << 31) +#define USB_CNTRX_NBLK_MSK (0x1FUL << 26) +#define USB_CNTRX_BLSIZE (0x1UL << 31) /*Set Channel/Endpoint to the USB Register */ @@ -686,20 +699,17 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; \ (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -869,16 +879,21 @@ uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); + +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); -HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, - uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); @@ -910,5 +925,4 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, } #endif /* __cplusplus */ - #endif /* STM32G0xx_LL_USB_H */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/README.md b/system/Drivers/STM32G0xx_HAL_Driver/README.md index 19c7bcf357..25f83db272 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/README.md +++ b/system/Drivers/STM32G0xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeG0 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32g0xx_hal_driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.4.7-brightgreen.svg) ## Overview diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html index 1ba7c1bd2d..a8856af3f5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32G0xx_HAL_Driver/Release_Notes.html @@ -39,11 +39,123 @@

Purpose

Update History

- +

Main Changes

Maintenance release

    +
  • HAL/LL ADC update +
      +
    • Adjust the ADC calibration procedure in the HAL_ADCEx_Calibration_Start() API.
      • +
    • Add a HAL unlock operation when the process exits with a TIMEOUT.
      • +
    • Fix LL_ADC_GetChannelSamplingTime() behavior when multiple channels are configured, ensuring the sampling time of the lowest channel number is correctly retrieved.
      • +
    • +
  • HAL COMP update +
      +
    • Update HAL_COMP_Init()API to prevent COMP3 initialization from disabling windowmode of COMP1 and COMP2.
      • +
    • +
  • HAL CRYP update +
      +
    • Remove calls to __HAL_UNLOCK() when __HAL_LOCK() has not been invoked.
      • +
    • Prevent out-of-bounds reads from local arrays for all data types.
      • +
    • +
  • HAL DAC update +
      +
    • Update the trimming factor to use a 6-bit width.
      • +
    • Add a workaround in HAL_DACEx_SelfCalibrate() API to check trimming value is always below maximum.
      • +
    • +
  • LL DMA update +
      +
    • Align LL_DMAMUX_MAX_REQ value for G0B0x devices with the reference manual.
      • +
    • +
  • HAL FDCAN update +
      +
    • Fix GetIndex computation overflow in overwrite mode in HAL_FDCAN_GetRxMessage() API.
      • +
    • Fix the assertion issue when the number of Standard or Extended filters is zero in HAL_FDCAN_ConfigFilter() API.
      • +
    • Fix confuse between two timeout definitions in HAL_FDCAN_Stop() API.
      • +
    • +
  • HAL I2C update +
      +
    • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
      • +
    • Improve HAL_I2C_IsDeviceReady() API to properly account for the number of trials.
      • +
    • Add a temporary variable in HAL_I2C_Master_Abort_IT() API to get I2C mode before comparison.
      • +
    • Move temporary variable declaration at the beginning in I2C_TransferCofig() function.
      +
      • +
    • +
  • HAL SMBUS update +
      +
    • Improve HAL_SMBUS_IsDeviceReady() API to properly account for the number of trials.
      • +
    • +
  • HAL/LL PWR update +
      +
    • Update HAL_PWREx_ConfigPVM() API to configure VDDIO2 voltage monitoring (disable, enable, bypass) per RM0444 Rev6, and declare HAL APIs for VDDUSB, VDDIO2, and PVMUSB control as deprecated.- Add new static inline APIs for VDDIO2 voltage monitoring: LL_PWR_SetPVM() and LL_PWR_GetPVM().
      • +
    • Mention that the legacy Power Voltage Monitoring configuration is depricated and kept only for backward compatibility.
      • +
    • +
  • HAL/LL SPI update +
      +
    • Add assertion in HAL_SPI_Transmit()/HAL_SPI_Receive() and HAL_SPI_TransmitReceive() APIs to ensure the data buffer is 16-bit aligned when DataSize is greater than 8 bits.
      • +
    • Add note to HAL_SPI_Receive() API to clarify its behavior in master mode.
      • +
    • Add units to physical measurement parameters.
      • +
    • Avoid buffer overflow in SPI_WaitFifoStateUntilTimeout() API.
      • +
    • +
  • HAL TIM update +
      +
    • Fix update flag (UIF) clearing in TIM_Base_SetConfig() API.
      • +
    • Update TIM_CCER_CCxE_MASK to support internal TIM Channel 5 and 6.
      • +
    • Fix complementary channel being systematically disabled by TIM_OCx_SetConfig() API.
      • +
    • +
  • HAL UART update +
      +
    • Update UART_RxISR_8BIT_FIFOEN() and UART_RxISR_16BIT_FIFOEN() functions to ensure Rx buffer is not written beyond boundaries.
      • +
    • Update wrong comment in HAL_UARTEx_DisableFifoMode() API.
      • +
    • Align default prescaler value in UART_GET_DIV_FACTOR macro with reference manual.
      • +
    • Update UART_DMAAbortOnError() function to correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
      • +
    • Update UART_DMAReceiveCplt() function to provide an accurate position parameter when ReceptionToIdle mode is used with DMA and UART/DMA interrupt handling is delayed.
      • +
    • Ensure HAL_UART_RXEVENT_IDLE is reported when using HAL_UARTEx_ReceiveToIdle_DMA() with circular DMA, even when the received data length is equal to the configured buffer size (or a multiple of it).
      • +
    • Provide an accurate position parameter in RxEventCallback when ReceptionToIdle mode is used with DMA and UART/DMA interrupt handling is delayed.
      • +
    • Fix transfer count underflow when using polling mode.
      • +
    • +
  • HAL/LL LPUART update- Add LL_LPUART_RequestTxDataFlush() static inline API allowing TX FIFO flush request. +
      +
    • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array
      • +
    • +
  • HAL/LL USART update +
      +
    • Align default prescaler value in USART_GET_DIV_FACTOR macro with reference manual.
      • +
    • Improve the visibility of the SPI function support in HAL USART description- Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array
      • +
    • +
  • LL UCPD update +
      +
    • Add LL_UCPD_IsActiveFlag_RxErr() API to read Rx error flag UCPD_SR_RXERR.
      • +
    • +
+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38
    • +
  • STM32CubeIDE toolchain V1.19.0
    • +
+

Supported Devices and boards

+

Supported Devices:

+
    +
  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • +
  • STM32G061xx, STM32G051xx, STM32G050xx
    • +
  • STM32G081xx, STM32G071xx, STM32G070xx
    • +
  • STM32G041xx, STM32G031xx, STM32G030xx
    • +
+

Backward Compatibility

+

This release is compatible with the previous versions.

+

Dependencies

+


+

+
+
+
+ +
+

Main Changes

+

Maintenance release

+
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
  • HAL/LL GENERIC update
      @@ -116,6 +228,7 @@

      Maintenance release

    • HAL FDCAN update
      • Fix GetIndex issue in HAL_FDCAN_GetRxMessage.
        • +
      • Remove shift from ‘FDCAN_DLC_BYTES_X’ definitions so that values taken by ‘DataLength’ structure member comply to the definition of a DLC.
    • HAL FLASH update
        @@ -192,13 +305,13 @@

        Known limitations

        • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38
        • STM32CubeIDE toolchain V1.14.0
        -

        Supported Devices and boards

        +

        Supported Devices and boards

        Supported Devices:

        • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
          • @@ -206,9 +319,9 @@

          Supported Devices and boards

        • STM32G081xx, STM32G071xx, STM32G070xx
        • STM32G041xx, STM32G031xx, STM32G030xx
        -

        Backward Compatibility

        +

        Backward Compatibility

        This release is compatible with the previous versions.

        -

        Dependencies

        +

        Dependencies


@@ -216,8 +329,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

  • General updates to fix known defects and enhancements implementation.
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
    • @@ -226,13 +339,13 @@

    Known limitations

    • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
    • STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
      • @@ -240,9 +353,9 @@

      Supported Devices and boards

    • STM32G081xx, STM32G071xx, STM32G070xx
    • STM32G041xx, STM32G031xx, STM32G030xx
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    -

    Dependencies

    +

    Dependencies


@@ -250,8 +363,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

  • General updates to fix known defects and enhancements implementation.

  • HAL/LL Drivers updates @@ -389,13 +502,13 @@

    Known limitations

    • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
    • STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
      • @@ -403,9 +516,9 @@

      Supported Devices and boards

    • STM32G081xx, STM32G071xx, STM32G070xx
    • STM32G041xx, STM32G031xx, STM32G030xx
    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    -

    Dependencies

    +

    Dependencies


@@ -413,8 +526,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

  • HAL/LL Drivers updates
      @@ -431,13 +544,13 @@

      Known limitations

      • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
      • STM32CubeIDE toolchain v1.7.0
      -

      Supported Devices and boards

      +

      Supported Devices and boards

      Supported Devices:

      • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
        • @@ -446,7 +559,7 @@

        Supported Devices and boards

      • STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility

      This release is compatible with the previous versions.

      -

      Dependencies

      +

      Dependencies


@@ -454,8 +567,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

  • General updates to fix known defects and enhancements implementation.

  • HAL/LL Drivers updates

    • @@ -589,13 +702,13 @@

    Known limitations

    • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
    • STM32CubeIDE toolchain v1.7.0
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
      • @@ -604,7 +717,7 @@

      Supported Devices and boards

    • STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility

    This release is compatible with the previous versions.

    -

    Dependencies

    +

    Dependencies


@@ -612,7 +725,7 @@

Dependencies

-

Main Changes

+

Main Changes

Patch release

Patch release of HAL and Low Layer drivers

Additional features

@@ -632,13 +745,13 @@

Known limitations

  • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
  • STM32CubeIDE toolchain v1.5.0
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • @@ -646,9 +759,9 @@

    Supported Devices and boards

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies


@@ -656,7 +769,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and Product Update

Official release of HAL and Low layers drivers introducing STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices and STM32G061xx/STM32G051xx/STM32G050xx devices.

Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.

@@ -1127,13 +1240,13 @@

Known limitations

  • USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.
-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
  • STM32CubeIDE toolchain v1.5.0
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G0C1xx, STM32G0B1xx, STM32G0B0xx
    • @@ -1141,9 +1254,9 @@

    Supported Devices and boards

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies


@@ -1151,8 +1264,8 @@

Dependencies

-

Main Changes

-

Maintenance release

+

Main Changes

+

Maintenance release

Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.

Fixed bugs list

@@ -1221,27 +1334,27 @@

Maintenance release

-

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and product update

First release of HAL and Low layers drivers to introduce support of STM32G041xx/STM32G031xx/STM32G030xx devices.

Maintenance release of HAL and Low layers drivers supporting STM32G081xx/STM32G071xx/STM32G070xx devices.

@@ -1328,27 +1441,27 @@

Maintenance release and produc -

Development Toolchains and Compilers

+

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7.2
-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx, STM32G071xx, STM32G070xx
  • STM32G041xx, STM32G031xx, STM32G030xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

Maintenance release and product update

Maintenance release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx devices.

Additional features

@@ -1437,32 +1550,32 @@

Maintenance release and produc -

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx
  • STM32G071xx
  • STM32G070xx
-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Dependencies

+

Dependencies

-

Main Changes

+

Main Changes

First release

First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx

-

Supported Devices and boards

+

Supported Devices and boards

Supported Devices:

  • STM32G081xx
  • STM32G071xx
  • STM32G070xx
-

Dependencies

+

Dependencies

diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c index f03e8946c8..5a322b7c54 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c @@ -55,13 +55,13 @@ /** * @brief STM32G0xx HAL Driver version number */ -#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ -#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\ +#define __STM32G0xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32G0xx_HAL_VERSION_SUB1 (0x04UL) /*!< [23:16] sub1 version */ +#define __STM32G0xx_HAL_VERSION_SUB2 (0x07UL) /*!< [15:8] sub2 version */ +#define __STM32G0xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24UL)\ + |(__STM32G0xx_HAL_VERSION_SUB1 << 16UL)\ + |(__STM32G0xx_HAL_VERSION_SUB2 << 8UL )\ |(__STM32G0xx_HAL_VERSION_RC)) #if defined(VREFBUF) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c index 35a512148e..484310a5b8 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c @@ -163,9 +163,11 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) } } - calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); + /* Read the calibration factor and increment by one */ + calibration_factor_accumulated += (LL_ADC_GetCalibrationFactor(hadc->Instance) + 1UL); } - /* Compute average */ + /* Compute average (rounded up to the nearest integer) */ + calibration_factor_accumulated += (calibration_index / 2UL); calibration_factor_accumulated /= calibration_index; /* Apply calibration factor (requires ADC enable and disable process) */ @@ -176,10 +178,13 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) { adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + /* Delay applied only when ADC clock frequency is much lower than CPU clock frequency + (in other cases, code execution time is sufficient to ensure necessary delay) */ if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16) { /* Delay loop initialization and execution */ - /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */ + /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format + (for instance, computation from ADC prescaler 64 (register bitfield value 0x9) will give decimal value 64) */ delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL)); /* Divide variable by 2 to compensate partially CPU processing cycles */ delay_cpu_cycles >>= 1UL; @@ -211,6 +216,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + __HAL_UNLOCK(hadc); + return HAL_ERROR; } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c index 5b5f3caa84..777217fe00 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c @@ -352,7 +352,13 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) else { CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE); - CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE); + + /* Note: In case of COMP3, COMP2 can also be used in window mode with */ + /* COMP1. Therefore, do not change windowmode parameter of COMP2 */ + if (hcomp->Instance != COMP3) + { + CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE); + } } /* Set window mode output */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c index d170c8b5a6..5f35215813 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c @@ -64,8 +64,8 @@ /** @defgroup CRC_Private_Functions CRC Private Functions * @{ */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength); /** * @} */ @@ -284,7 +284,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -304,11 +304,12 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; @@ -336,7 +337,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -361,12 +362,13 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: @@ -429,7 +431,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ uint16_t data; @@ -452,13 +454,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if ((BufferLength % 4U) == 2U) + else if ((BufferLength % 4U) == 2U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if ((BufferLength % 4U) == 3U) + else if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ @@ -466,6 +468,10 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } + else + { + /* Nothing to do */ + } } /* Return the CRC computed value */ @@ -480,7 +486,7 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ __IO uint16_t *pReg; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c index 37b78f407b..b4d36ab815 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c index 590a5a6803..f4a76af503 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp.c @@ -629,9 +629,6 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD } else { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Busy error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; return HAL_ERROR; @@ -685,9 +682,6 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD } else { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Busy error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; return HAL_ERROR; @@ -928,8 +922,6 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) hcryp->SuspendRequest = HAL_CRYP_SUSPEND; } - - /** * @brief CRYP processing suspension and peripheral internal parameters storage. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -1874,23 +1866,23 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) uint32_t itflag = hcryp->Instance->SR; /* Check if error occurred */ - if ((itsource & CRYP_IT_ERRIE) != RESET) + if ((itsource & CRYP_IT_ERRIE) == CRYP_IT_ERRIE) { /* If write Error occurred */ - if ((itflag & CRYP_IT_WRERR) != RESET) + if ((itflag & CRYP_IT_WRERR) == CRYP_IT_WRERR) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if ((itflag & CRYP_IT_RDERR) != RESET) + if ((itflag & CRYP_IT_RDERR) == CRYP_IT_RDERR) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } } - if ((itflag & CRYP_IT_CCF) != RESET) + if ((itflag & CRYP_IT_CCF) == CRYP_IT_CCF) { - if ((itsource & CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) == CRYP_IT_CCFIE) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2521,10 +2513,11 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2630,7 +2623,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2871,7 +2864,7 @@ static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t i; /* Write the input block in the IN FIFO */ @@ -2933,7 +2926,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) @@ -3087,7 +3080,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; uint32_t npblb; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t index; uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ @@ -3295,10 +3288,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -3764,7 +3758,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4] ; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ @@ -3967,10 +3961,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4420,7 +4415,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; @@ -4578,7 +4573,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t count; uint32_t reg; @@ -4711,10 +4706,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4872,10 +4868,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4995,10 +4992,11 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { @@ -5223,7 +5221,6 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout do { - count-- ; if (count == 0U) { /* Disable the CRYP peripheral clock */ @@ -5243,7 +5240,10 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout /*Call legacy weak error callback*/ HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + return; } + count--; } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c index f7c8fcf44d..4ff833b2bb 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c @@ -95,7 +95,8 @@ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout) { uint32_t tickstart; /* Assume first Init.HeaderSize is in words */ @@ -216,7 +217,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; uint32_t tickstart; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c index 7347d8531c..3c335a9b7e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c @@ -998,7 +998,10 @@ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) uint32_t result; /* Check the DAC peripheral handle */ - assert_param(hdac != NULL); + if (hdac == NULL) + { + return (uint32_t)HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c index 0d5c73179c..497bd07b0a 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c @@ -459,8 +459,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -506,8 +506,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -580,8 +584,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c index a2b906a7d5..fe03b9160e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c @@ -524,15 +524,15 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) } else { + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); @@ -582,12 +582,12 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) } else { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - /* Disable the channel */ __HAL_DMA_DISABLE(hdma); + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; @@ -806,51 +806,51 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ #if defined(DMA2) - hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); #else - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); #endif /* DMA2 */ - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ - if (hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) { - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - if (hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } + if (hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } } /* Transfer Error Interrupt management **************************************/ @@ -1006,7 +1006,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca */ - /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c index 28309c9b1f..630d19e82c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c @@ -92,7 +92,7 @@ * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); @@ -142,7 +142,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, - HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) + const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) { HAL_StatusTypeDef status; HAL_DMA_StateTypeDef temp_state = hdma->State; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c index 35bba78b6d..ceb961d456 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c @@ -140,7 +140,7 @@ * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; @@ -262,9 +262,9 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -552,9 +552,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * @arg @ref EXTI_TRIGGER_FALLING * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -596,7 +596,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @arg @ref EXTI_TRIGGER_FALLING * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -632,7 +632,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti) { __IO uint32_t *regaddr; uint32_t maskline; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c index 08c445d76b..8216b8de7a 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_fdcan.c @@ -1309,7 +1309,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); @@ -2024,18 +2024,21 @@ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) */ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) { - uint32_t Counter = 0U; + uint32_t tickstart; if (hfdcan->State == HAL_FDCAN_STATE_BUSY) { /* Request initialisation */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until the INIT bit into CCCR register is set */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) { /* Check for the Timeout */ - if (Counter > FDCAN_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; @@ -2045,22 +2048,19 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) return HAL_ERROR; } - - /* Increment counter */ - Counter++; } - /* Reset counter */ - Counter = 0U; - /* Exit from Sleep mode */ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until FDCAN exits sleep mode */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) { /* Check for the Timeout */ - if (Counter > FDCAN_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; @@ -2070,9 +2070,6 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) return HAL_ERROR; } - - /* Increment counter */ - Counter++; } /* Enable configuration change */ @@ -2224,7 +2221,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex = 0; + uint32_t GetIndex; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2244,19 +2241,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 0 element index */ + GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) & SRAMCAN_RF0_NBR; } } - /* Calculate Rx FIFO 0 element index */ - GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); - /* Calculate Rx FIFO 0 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } @@ -2273,18 +2271,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 1 element index */ + GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) & SRAMCAN_RF1_NBR; } } - /* Calculate Rx FIFO 1 element index */ - GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c index b31c687f0d..299be4df1a 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c @@ -494,7 +494,7 @@ uint32_t HAL_FLASHEx_FlashEmptyCheck(void) /** * @brief Force Empty check value. * @note Allows to modify program empty check value in order to force this - * infrmation in Flash Interface, for all next reset that do not launch + * information in Flash Interface, for all next reset that do not launch * Option Byte Loader. * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check * @retval None diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c index 4b4cc8a16f..853044b111 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c @@ -159,7 +159,7 @@ * the configuration information for the specified GPIO peripheral. * @retval None */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init) { uint32_t position = 0x00u; uint32_t iocurrent; @@ -283,7 +283,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) @@ -328,7 +328,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFuL << ((position & 0x07u) * 4u)) ; /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); @@ -364,10 +364,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @brief Read the specified input port pin. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family * @param GPIO_Pin specifies the port bit to read. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; @@ -394,7 +394,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin @@ -421,7 +421,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin * @brief Toggle the specified GPIO pin. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family * @param GPIO_Pin specifies the pin to be toggled. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) @@ -446,7 +446,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * until the next reset. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family * @param GPIO_Pin specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c index 97f288aedb..ef6ca9f27c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_hcd.c @@ -46,6 +46,9 @@ (#)Enable HCD transmission and reception: (##) HAL_HCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -169,9 +172,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Init Host */ (void)USB_HostInit(hhcd->Instance, hhcd->Init); - /* Deactivate the power down */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - hhcd->State = HAL_HCD_STATE_READY; /* Host Port State */ @@ -219,6 +219,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, __HAL_LOCK(hhcd); + if (ch_num > 16U) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[0U].pmaaddr1; + + hhcd->phy_chin_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + hhcd->phy_chout_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + /* Check if the logical channel are already allocated */ used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num); @@ -231,6 +252,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* No free Channel available, return error */ if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -267,6 +289,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -285,6 +308,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -302,22 +326,28 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + /* This is a dual EP0 PMA allocation */ + hhcd->ep0_PmaAllocState |= (0x1UL << 12); + /* PMA Dynamic Allocation for EP0 OUT direction */ hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -327,6 +357,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -352,6 +383,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -730,12 +762,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { uint8_t phy_chnum; - uint8_t chnum; - uint32_t epch_reg; + uint8_t ch_dir; uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance); /* check if this is an USB pending IT */ - if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U) + if ((SYSCFG->IT_LINE_SR[8] & (0x1UL << 2)) == 0U) { return; } @@ -755,50 +786,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Correct Transaction Detected -------*/ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) { - /* Handle Host channel Interrupt */ - for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++) - { - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); + /* Get Physical channel */ + phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /* Call Channel_IN_IRQ() */ - HCD_HC_IN_IRQHandler(hhcd, chnum); - } - else - { - /*Channel was not closed correctly still have interrupt */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) | - (USB_CH_VTTX | USB_CH_ERRTX); + /* Get channel direction */ + ch_dir = (uint8_t)__HAL_HCD_GET_CHDIR(hhcd); - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } - - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); - - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /*Call Channel_OUT_IRQ()*/ - HCD_HC_OUT_IRQHandler(hhcd, chnum); - } - else - { - /* Clear Error & unwanted VTTX or Channel was not closed correctly */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) | - (USB_CH_VTRX | USB_CH_ERRRX); - - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } + if (ch_dir == CH_OUT_DIR) + { + /* Call Channel_OUT_IRQ() */ + HCD_HC_OUT_IRQHandler(hhcd, phy_chnum); + } + else + { + /* Call Channel_IN_IRQ() */ + HCD_HC_IN_IRQHandler(hhcd, phy_chnum); } return; @@ -1019,8 +1021,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); if (hhcd->State == HAL_HCD_STATE_READY) { @@ -1090,8 +1090,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -1115,9 +1113,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - /* Setup Legacy weak Callbacks */ if (hhcd->State == HAL_HCD_STATE_READY) { @@ -1190,8 +1185,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -1215,9 +1208,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = pCallback; @@ -1231,9 +1221,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } @@ -1248,9 +1235,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ @@ -1264,9 +1248,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ @@ -1298,16 +1279,21 @@ transfers. */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { + __IO uint32_t count = HCD_PDWN_EXIT_CNT; + __HAL_LOCK(hhcd); - /*Set the PullDown on the PHY */ - hhcd->Instance->BCDR |= USB_BCDR_DPPD; + /* Remove PowerDown */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - /* Clear Reset */ - hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; + /* Few cycles to ensure exit from powerdown */ + while (count > 0U) + { + count--; + } - /*Remove PowerDown */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + /* Clear Reset */ + hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; __HAL_UNLOCK(hhcd); @@ -1554,6 +1540,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } +/** + * @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} + #if (USE_USB_DOUBLE_BUFFER == 1U) /** * @brief Handle Host Channel OUT Double Buffer Bulk requests. @@ -1863,16 +1867,17 @@ static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /** * @brief Handle Host Channel IN interrupt requests. * @param hhcd HCD handle - * @param ch_num Channel number - * This parameter can be a value from 1 to 15 + * @param chnum Channel number + * This parameter can be a value from 1 to 8 * @retval none */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { uint16_t received_bytes; - uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + uint8_t phy_chnum = chnum; + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); - /*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); /* Manage Correct Transaction */ @@ -1914,8 +1919,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) { - hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; } else { @@ -1928,10 +1933,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; } } - /* manage NACK Response */ + /* Manage NACK Response */ else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) { @@ -1945,7 +1950,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); } } - /* manage STALL Response */ + /* Manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { (void)HAL_HCD_HC_Halt(hhcd, ch_num); @@ -2013,16 +2018,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) * @brief Handle Host Channel OUT interrupt requests. * @param hhcd HCD handle * @param chnum Channel number - * This parameter can be a value from 1 to 15 + * This parameter can be a value from 1 to 8 * @retval none */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - uint16_t data_xfr; __IO uint32_t WregCh; + uint16_t data_xfr; + uint8_t phy_chnum = chnum; - /* Get Physical Channel number */ - uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + /* Get Virtual Channel number */ + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */ uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); @@ -2033,7 +2039,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Handle Isochronous channel */ if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) { - /* correct transaction */ + /* Correct transaction */ if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) { /* Double buffer isochronous out */ @@ -2042,7 +2048,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); } #if (USE_USB_DOUBLE_BUFFER == 1U) - else /* double buffer isochronous out */ + else /* Double buffer isochronous out */ { /* Odd Transaction */ if ((ch_reg & USB_CH_DTOG_TX) != 0U) @@ -2060,8 +2066,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* Transfer complete state */ - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; } /*Clear Correct Transfer */ @@ -2069,9 +2075,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /*TX COMPLETE*/ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -2082,37 +2088,37 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); - if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr) + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) { - hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; } else { - hhcd->hc[chnum & 0xFU].xfer_len = 0U; + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; } /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ - if (hhcd->hc[chnum & 0xFU].xfer_len != 0U) + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { - /* manage multiple Xfer */ - hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr; - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + /* Manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; - /* start a new transfer */ - (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]); + /* Start a new transfer */ + (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else { /* Transfer complete */ - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; - - if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR)) - { - hhcd->hc[chnum & 0xFU].toggle_out ^= 1U; - } + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; } } /* Check NACK Response */ @@ -2120,41 +2126,41 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) { /* Update Channel status */ - hhcd->hc[chnum & 0xFU].state = HC_NAK; - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; - hhcd->hc[chnum & 0xFU].ErrCnt = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); - /*clear NAK status*/ + /* Clear NAK status */ WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; /* Update channel register Value */ HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh); - if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U) + if (hhcd->hc[ch_num & 0xFU].doublebuffer == 0U) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Check STALL Response */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) { - (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum); - hhcd->hc[chnum & 0xFU].state = HC_STALL; - hhcd->hc[chnum & 0xFU].urb_state = URB_STALL; + (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Check double buffer ACK in case of bulk transaction */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) { /* Double buffer management Bulk Out */ - (void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg); + (void) HCD_HC_OUT_BulkDb(hhcd, ch_num, (uint8_t)phy_chnum, ch_reg); } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ else @@ -2165,38 +2171,38 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); - } /* end no isochronous */ + } /* End no isochronous */ } /*------ Manage Transaction Error------*/ else { - hhcd->hc[chnum & 0xFU].ErrCnt++; - if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U) + hhcd->hc[ch_num & 0xFU].ErrCnt++; + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) { HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); - hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR; + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; } else { - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; } - hhcd->hc[chnum & 0xFU].state = HC_XACTERR; + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; - /*Clear ERR_TX*/ + /* Clear ERR_TX */ HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } @@ -2209,8 +2215,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - uint32_t FnrReg = hhcd->Instance->FNR; uint32_t IstrReg = hhcd->Instance->ISTR; + uint32_t FnrReg = hhcd->Instance->FNR; /* SE0 detected USB Disconnected state */ if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) @@ -2218,13 +2224,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /* Host Port State */ hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ + /* Clear all allocated virtual channel */ HAL_HCD_ClearPhyChannel(hhcd); /* Reset the PMA current pointer */ (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 Pma allocation state */ + /* Reset Ep0 Pma allocation state */ hhcd->ep0_PmaAllocState = 0U; /* Disconnection Callback */ @@ -2553,7 +2559,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) while ((j <= 31U) && (FreeBlocks != NbrReqBlocks)) { /* check if block j is free */ - if ((Entry & ((uint32_t)1U << j)) == 0U) + if ((Entry & ((uint32_t)1UL << j)) == 0U) { if (FreeBlocks == 0U) { @@ -2564,7 +2570,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) j++; /* Parse Column PMALockTable */ - while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) + while ((j <= 31U) && ((Entry & ((uint32_t)1UL << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) { FreeBlocks++; j++; @@ -2572,7 +2578,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) /* Free contiguous Blocks not found */ if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) || - ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U))) + ((j == 31U) && ((Entry & ((uint32_t)1UL << j)) != 0U))) { FreeBlocks = 0U; } @@ -2590,7 +2596,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) { for (uint8_t j = ColIndex; j <= 31U; j++) { - hhcd->PMALookupTable[i] |= ((uint32_t)1U << j); + hhcd->PMALookupTable[i] |= ((uint32_t)1UL << j); if (--FreeBlocks == 0U) { break; @@ -2632,7 +2638,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* Get a FreePMA Address */ pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps); - /* if there is no free space to allocate */ + /* If there is no free space to allocate */ if (pma_addr0 == 0xFFFFU) { return HAL_ERROR; @@ -2647,8 +2653,9 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hc->ep_num == 0U) { - hhcd->ep0_PmaAllocState = ch_num; - hhcd->ep0_PmaAllocState |= (1U << 8); + hhcd->ep0_PmaAllocState &= 0xFFF0U; + hhcd->ep0_PmaAllocState |= ch_num; + hhcd->ep0_PmaAllocState |= (1UL << 8); } /* Configure the PMA */ @@ -2781,7 +2788,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd) /* Allocate a Space for buffer descriptor table depending on the Host channel number */ for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++) { - hhcd->PMALookupTable[0] |= ((uint32_t)1U << i); + hhcd->PMALookupTable[0] |= ((uint32_t)1UL << i); } return HAL_OK; @@ -2843,12 +2850,12 @@ static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_ for (uint8_t j = ColIndex; j <= 31U; j++) { /* Check if the block is not already reserved or it was already closed */ - if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U) + if ((hhcd->PMALookupTable[i] & ((uint32_t)1UL << j)) == 0U) { return HAL_ERROR; } /* Free the reserved block by resetting the corresponding bit */ - hhcd->PMALookupTable[i] &= ~(1U << j); + hhcd->PMALookupTable[i] &= ~(1UL << j); if (--block_nbr == 0U) { diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c index 7107a410c7..a9e90748fc 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1407,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1428,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1439,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1451,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -3312,33 +3324,46 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ @@ -4552,7 +4577,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4561,7 +4586,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -6335,7 +6362,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6491,7 +6518,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6939,7 +6966,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6979,7 +7006,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7018,7 +7045,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7096,7 +7123,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7263,15 +7290,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c index 497b866f8e..96e0da0e88 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2s.c @@ -770,15 +770,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -889,15 +888,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -987,15 +985,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1014,6 +1011,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->TxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1024,7 +1023,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1053,15 +1051,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1080,6 +1077,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u hi2s->RxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable RXNE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1090,7 +1089,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1117,15 +1115,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1167,12 +1164,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Tx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) @@ -1181,7 +1173,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1208,15 +1206,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1264,12 +1261,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Rx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) @@ -1278,7 +1270,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1619,7 +1617,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1630,7 +1628,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c index 420e0894e0..3a6fd84c09 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd.c @@ -49,6 +49,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -311,8 +314,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); if (hpcd->State == HAL_PCD_STATE_READY) { @@ -390,8 +391,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -416,9 +415,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - /* Setup Legacy weak Callbacks */ if (hpcd->State == HAL_PCD_STATE_READY) { @@ -499,8 +495,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -524,9 +518,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = pCallback; @@ -540,9 +531,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -556,9 +544,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ @@ -572,9 +557,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -598,9 +580,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = pCallback; @@ -614,9 +593,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -630,9 +606,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ @@ -646,9 +619,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -672,9 +642,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = pCallback; @@ -688,9 +655,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -705,9 +669,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ @@ -721,9 +682,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -747,9 +705,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = pCallback; @@ -763,9 +718,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -780,9 +732,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ @@ -796,10 +745,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; + return status; } /** @@ -821,9 +767,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = pCallback; @@ -837,9 +780,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -853,9 +793,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ @@ -869,9 +806,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -894,9 +828,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = pCallback; @@ -910,9 +841,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -926,9 +854,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ @@ -942,9 +867,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ @@ -1009,7 +931,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); /* check if this is an USB pending IT */ - if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U) + if ((SYSCFG->IT_LINE_SR[8] & (0x1UL << 2)) == 0U) { return; } @@ -1395,7 +1317,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1410,7 +1332,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1732,6 +1654,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ @@ -1776,6 +1703,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -1796,27 +1735,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1882,7 +1821,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -1895,6 +1833,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -1936,7 +1875,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2012,7 +1951,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2044,11 +1983,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2098,6 +2037,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2109,10 +2054,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2143,7 +2090,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2171,6 +2118,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2183,10 +2136,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2216,7 +2171,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2225,7 +2180,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2233,13 +2188,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd_ex.c index 2819a349b8..3f67736b96 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd_ex.c @@ -82,7 +82,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { PCD_EPTypeDef *ep; - /* initialize ep structure*/ + /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; @@ -97,6 +97,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Single Buffer */ ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } @@ -105,6 +106,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; + /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); @@ -124,13 +126,11 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USB_DRD_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; - /* Enable BCD feature */ - USBx->BCDR |= USB_BCDR_BCDEN; - - /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); - USBx->BCDR |= USB_BCDR_DCDEN; + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; return HAL_OK; } @@ -162,21 +162,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) uint32_t tickstart = HAL_GetTick(); /* Wait for Min DCD Timeout */ - HAL_Delay(300U); + HAL_Delay(350U); - /* Data Pin Contact ? Check Detect flag */ - if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_PDEN); HAL_Delay(50U); @@ -242,7 +231,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +267,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c index 96ac916ee4..24b1436abf 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c @@ -112,7 +112,12 @@ *** PVM configuration *** ========================= - [..] + (+) The PVM is used to monitor the VDDIO2 power supply by comparing it to + 1.2 V threshold (PVM_VDDIO2[2:0] in PWR CR2 register). + (+) PVMOVDDIO2 flag is available to indicate if VDDIO2 is higher or lower + than the 1.2 threshold. This event is internally connected to the EXTI + line 34 and can generate an interrupt if enabled. + (+) This feature is supported on STM32G0C1xx and STM32G0B1xx devices. @endverbatim * @{ @@ -184,7 +189,7 @@ void HAL_PWREx_DisablePORMonitorSampling(void) * one in order to avoid having always PVDO output set. * @retval HAL_OK */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); @@ -250,6 +255,10 @@ void HAL_PWREx_DisablePVD(void) /** * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_EnableVddUSB(void) @@ -259,6 +268,10 @@ void HAL_PWREx_EnableVddUSB(void) /** * @brief Disable VDDUSB supply. + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev 6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_DisableVddUSB(void) @@ -271,6 +284,10 @@ void HAL_PWREx_DisableVddUSB(void) /** * @brief Enable VDDIO2 supply. * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev 6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_EnableVddIO2(void) @@ -281,6 +298,10 @@ void HAL_PWREx_EnableVddIO2(void) /** * @brief Disable VDDIO2 supply. + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev 6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_DisableVddIO2(void) @@ -292,6 +313,10 @@ void HAL_PWREx_DisableVddIO2(void) #if defined (PWR_PVM_SUPPORT) /** * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev 6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_EnablePVMUSB(void) @@ -301,6 +326,10 @@ void HAL_PWREx_EnablePVMUSB(void) /** * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @note For STM32G0C1xx and STM32G0B1xx devices, this function is deprecated and retained only to ensure backward compatibility. + * Power Voltage Monitoring configuration is now handled by the HAL_PWREx_ConfigPVM() API. + * The USV, IOSV, and PVMENUSB bits have been merged into the PVM_VDDIO2 bitfield of the PWR_CR2 register. + * Please refer to RM0444 Rev 6 or later, section "Power control register 2 (PWR_CR2)". * @retval None */ void HAL_PWREx_DisablePVMUSB(void) @@ -311,31 +340,36 @@ void HAL_PWREx_DisablePVMUSB(void) #if defined(PWR_PVM_SUPPORT) /** - * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @brief Configure the Power Voltage Monitoring (PVM). * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. * @note The API configures a single PVM according to the information contained * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. + * @note The API configures the voltage monitoring for the USB peripheral, + * which is on the VDDIO2 domain(refer to the device's datasheet). * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each * detection level and to each monitored supply. * @retval HAL status */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); - assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); /* Configure EXTI 34 interrupts if so required: scan through PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { - case PWR_PVM_USB: + case PWR_PVM_ENABLE: + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + /* Enable the Power Voltage Monitoring */ + MODIFY_REG(PWR->CR2, PWR_CR2_PVM_VDDIO2, PWR_PVM_ENABLE); + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM_EXTI_DISABLE_IT(); @@ -366,6 +400,16 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) } break; + case PWR_PVM_BYPASS: + /* Bypass the Power Voltage Monitoring */ + MODIFY_REG(PWR->CR2, PWR_CR2_PVM_VDDIO2, PWR_PVM_BYPASS); + break; + + case PWR_PVM_DISABLE: + /* Disable the Power Voltage Monitoring */ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVM_VDDIO2); + break; + default: status = HAL_ERROR; break; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c index 38a6175e52..64b8b710b5 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c @@ -306,7 +306,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then to LSE On or LSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t temp_sysclksrc; @@ -802,7 +802,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c index a8b6d376fe..a6c3352658 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c @@ -109,7 +109,7 @@ * * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit) { uint32_t tmpregister; uint32_t tickstart; @@ -1215,7 +1215,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct = {0}; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; @@ -1367,7 +1367,7 @@ void HAL_RCCEx_DisableLSCO(void) * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit) { uint32_t value; /* no init needed */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c index ee8559977b..a135fc70ad 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc.c @@ -397,7 +397,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) } /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= 0x00000000U; + hrtc->Instance->CR = 0x00000000U; hrtc->Instance->WUTR = RTC_WUTR_WUT; hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); hrtc->Instance->ALRMAR = 0x00000000U; @@ -774,7 +774,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim { if(Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -794,7 +794,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -860,7 +860,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1499,7 +1499,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1728,7 +1728,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc) { /* Return RTC handle state */ return hrtc->State; @@ -1901,7 +1901,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc) { return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c index 827b4179fe..41294c930e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rtc_ex.c @@ -477,9 +477,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 { uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) + while(READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) + if(READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U) { /* Clear the TIMESTAMP OverRun Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); @@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + while(READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -631,7 +631,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + while(READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -702,7 +702,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + while(READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -748,7 +748,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) + if(READ_BIT(RTC->SR, RTC_SR_WUTF) != 0U) { /* Clear the WAKEUPTIMER interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); @@ -792,7 +792,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) + while(READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) { if(Timeout != HAL_MAX_DELAY) { diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c index 5380da57b5..d90be4750f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard.c @@ -2406,7 +2406,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c index 2bf6ff5ef5..f51191063d 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus.c @@ -1543,55 +1543,50 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Reset the error code for next trial */ + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials == Trials) - { - /* Generate Stop */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) == HAL_OK) { - return HAL_ERROR; + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } /* Increment Trials */ SMBUS_Trials++; } while (SMBUS_Trials < Trials); + /* Update SMBUS state */ hsmbus->State = HAL_SMBUS_STATE_READY; /* Update SMBUS error code */ @@ -1959,7 +1954,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2387,7 +2382,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c index d576a27e34..53a1d4170e 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c index d40532656b..68c8d4e5de 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -67,6 +68,14 @@ does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() + [..] + Data buffer address alignment restriction: + (#) There is no support for unaligned accesses on the Cortex-M0 processor. + If the user wants to transfer in 16Bit data mode, it shall ensure that 16-bit aligned address is used for: + (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT() + (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT() + (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA() + and HAL_SPI_TransmitReceive_DMA(). [..] Callback registration: @@ -190,7 +199,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,43 +823,47 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +902,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +912,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +921,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -919,7 +933,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -928,7 +942,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -937,9 +951,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -964,29 +978,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -996,12 +1012,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1011,17 +1037,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1093,9 +1113,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1117,9 +1137,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1136,8 +1156,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1155,8 +1175,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1182,8 +1203,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1209,32 +1231,31 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint32_t tmp_mode; @@ -1250,14 +1271,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1271,18 +1296,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1294,7 +1321,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1334,7 +1361,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1357,7 +1384,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1388,9 +1415,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1399,7 +1426,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -1421,7 +1448,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1452,9 +1479,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1468,8 +1495,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1494,8 +1522,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1511,43 +1540,51 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1555,14 +1592,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1571,7 +1606,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1619,27 +1654,35 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1650,12 +1693,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1727,24 +1764,31 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1754,16 +1798,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1777,7 +1820,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1838,21 +1881,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1860,25 +1901,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1940,9 +1979,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1952,16 +1991,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1969,22 +2008,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2001,12 +2042,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2084,9 +2119,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2096,34 +2131,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2132,26 +2166,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2160,7 +2193,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2251,9 +2284,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2272,9 +2305,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2283,16 +2316,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2385,7 +2419,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2418,7 +2453,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2673,9 +2709,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -2965,7 +3003,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -2977,7 +3015,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3004,7 +3042,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3061,7 +3099,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3178,7 +3216,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3216,7 +3254,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3278,7 +3317,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3296,7 +3335,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3314,7 +3353,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3332,7 +3371,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3355,7 +3394,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3377,7 +3416,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3393,7 +3432,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3443,7 +3483,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3460,7 +3500,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3511,8 +3552,10 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in packing mode */ if (hspi->RxXferCount > 1U) { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); - hspi->pRxBuffPtr += sizeof(uint16_t); + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) { @@ -3593,20 +3636,10 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - /* Transmit data in packing Bit mode */ - if (hspi->TxXferCount >= 2U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } /* Transmit data in 8 Bit mode */ - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) @@ -3697,7 +3730,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3850,7 +3883,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3876,7 +3909,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3955,7 +3988,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -3978,7 +4014,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4037,7 +4073,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4333,7 +4372,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4376,7 +4416,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4405,7 +4446,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c index b7a3213501..e3a12f63e2 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c @@ -4586,7 +4586,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t ((BurstLength) >> 8U) + 1U); - return status; } @@ -6984,8 +6983,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -6998,16 +6995,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + /* Ensure that the update event is generated before writing back CR1 register with URS = 0 */ + __DSB(); + + TIMx->CR1 = tmpcr1; } /** @@ -7050,12 +7049,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7126,12 +7126,13 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7201,12 +7202,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7553,9 +7555,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7599,9 +7610,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7643,9 +7663,18 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7682,9 +7711,18 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7726,9 +7764,18 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7774,9 +7821,13 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7863,10 +7914,10 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c index ee268d8bf7..d2b8dc02b7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c @@ -2663,9 +2663,9 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -2824,9 +2824,9 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_alarm_template.c index 8f3f9a9230..4231328df4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_alarm_template.c @@ -33,7 +33,7 @@ HAL_RTC_MODULE_ENABLED define in stm32g0xx_hal_conf.h [..] - (@) HAL RTC alarm and HAL RTC wakeup drivers cant be used with low power modes: + (@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes: The wake up capability of the RTC may be intrusive in case of prior low power mode configuration requiring different wake up sources. Application/Example behavior is no more guaranteed diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_wakeup_template.c index 4774ef4604..ba2ed9dcb7 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_wakeup_template.c @@ -34,7 +34,7 @@ HAL_RTC_MODULE_ENABLED define in stm32g0xx_hal_conf.h [..] - (@) HAL RTC alarm and HAL RTC wakeup drivers cant be used with low power modes: + (@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes: The wake up capability of the RTC may be intrusive in case of prior low power mode configuration requiring different wake up sources. Application/Example behavior is no more guaranteed diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_tim_template.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_tim_template.c index 5a28f6dd05..e8d981466c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_tim_template.c @@ -57,6 +57,9 @@ TIM_HandleTypeDef TimHandle = {.Init = {0}}; /* Private function prototypes -----------------------------------------------*/ void TIM14_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /** @@ -119,6 +122,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Start the TIM time Base generation in interrupt mode */ if (HAL_TIM_Base_Start_IT(&TimHandle) == HAL_OK) { @@ -186,8 +193,15 @@ void HAL_ResumeTick(void) * @param htim TIM handle * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + HAL_IncTick(); } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c index 292c78f35f..2a11b5d0f9 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c @@ -1022,75 +1022,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1184,7 +1188,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1296,7 +1308,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1800,10 +1820,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1870,9 +1886,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } } - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1935,9 +1948,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } } - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2063,10 +2073,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2146,8 +2152,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2167,9 +2171,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2243,9 +2244,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2271,9 +2269,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2521,6 +2516,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3697,8 +3714,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->TxXferCount = 0U; - /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3749,8 +3764,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->RxXferCount = 0U; - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3777,12 +3790,22 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3815,12 +3838,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3852,7 +3885,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3860,7 +3892,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3884,8 +3915,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3919,10 +3948,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3974,10 +3999,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4015,8 +4036,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4048,8 +4067,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -4556,6 +4573,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4720,6 +4738,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c index 29e6724369..9e8b1c356c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,15 +253,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -341,19 +339,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -361,13 +359,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -576,7 +574,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -990,17 +988,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c index 243b93d3af..b5357aa084 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -225,8 +225,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -238,7 +238,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -657,11 +657,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3052,7 +3051,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c index c645b6817c..09ab541e7c 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c index 24aa073a48..605c2c7793 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c @@ -237,7 +237,7 @@ * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef const *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c index cb0ffd21b8..10316fbfa4 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c @@ -57,7 +57,7 @@ /* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ @@ -67,7 +67,7 @@ /* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -93,7 +93,7 @@ ) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \ - (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC4) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3) \ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c index ec32fc8aad..433ff9e1db 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c @@ -1,12 +1,12 @@ /** ****************************************************************************** - * @file stm32g0xx_ll_crs.h + * @file stm32g0xx_ll_crs.c * @author MCD Application Team * @brief CRS LL module driver. ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. + * Copyright (c) 2018 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -15,6 +15,7 @@ * ****************************************************************************** */ + #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ @@ -61,7 +62,6 @@ ErrorStatus LL_CRS_DeInit(void) } - /** * @} */ diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c index ba4793dbe8..040d3331db 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c @@ -111,7 +111,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef const *GPIOx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c index 3575197894..de214a5079 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c @@ -187,7 +187,7 @@ ErrorStatus LL_RCC_DeInit(void) {} /* Reset PLLCFGR register */ - LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); + LL_RCC_WriteReg(PLLCFGR, 16UL << RCC_PLLCFGR_PLLN_Pos); /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c index 3d3c105116..93ae286a88 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c @@ -99,7 +99,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c index b724a55636..204535ad8f 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c @@ -130,7 +130,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -179,8 +179,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -367,7 +368,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } @@ -382,7 +383,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) * - SUCCESS: SPI registers are Initialized * - ERROR: SPI registers are not Initialized */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct) { uint32_t i2sdiv = 2U; uint32_t i2sodd = 0U; diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c index 151a31b345..760b51b857 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c @@ -603,8 +603,6 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor * interface configuration data structure) diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c index 7e295ad4cd..d96ba814b2 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c @@ -125,7 +125,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) * the configuration information for the UCPD peripheral. * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c index da131b227f..f673b6fd1b 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -55,6 +58,7 @@ /* Private functions ---------------------------------------------------------*/ static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); +#if defined (HAL_HCD_MODULE_ENABLED) #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, @@ -65,6 +69,7 @@ static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, uint32_t len); #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Reset the USB Core (needed after USB clock settings change) @@ -358,6 +363,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -462,7 +471,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -564,9 +573,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -598,19 +607,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -619,15 +634,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -638,18 +651,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -693,26 +696,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -1003,14 +1003,14 @@ HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) /* Clear All Pending Interrupt */ USBx->ISTR = 0U; + /* Set the PullDown on the PHY */ + USBx->BCDR |= USB_BCDR_DPPD; + /* Enable Global interrupt */ USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); - /* Remove Reset */ - USBx->CNTR &= ~USB_CNTR_USBRST; - return HAL_OK; } @@ -1064,33 +1064,7 @@ uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) return USBx->FNR & 0x7FFU; } -/** - * @brief Set the channel Kind (Single/double buffer mode) - * @param USBx Selected device - * @param phy_ch_num Selected device - * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, - uint8_t phy_ch_num, uint8_t db_state) -{ - uint32_t tmp; - - if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) - { - tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; - } - else - { - tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; - } - - /* Set the device speed in case using HUB FS with device LS */ - USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); - - return HAL_OK; -} - +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -1126,7 +1100,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; - /* initialize host Channel */ + /* Initialize host Channel */ switch (ep_type) { case EP_TYPE_CTRL: @@ -1150,7 +1124,17 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, break; } - wChRegVal &= ~USB_CHEP_DEVADDR; + /* Clear device address, Endpoint number and Low Speed Endpoint fields */ + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFUL << 27)); + + /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | ((uint32_t)epnum & 0x0FU)); @@ -1163,12 +1147,39 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal |= USB_CHEP_LSEP; } - /* Set the dev_address & ep type */ + /* Update the channel register value */ USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); return ret; } +/** + * @brief Set the channel Kind (Single/double buffer mode) + * @param USBx Selected device + * @param phy_ch_num Selected device + * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, + uint8_t phy_ch_num, uint8_t db_state) +{ + uint32_t tmp; + + if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) + { + tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); + + return HAL_OK; +} + /** * @brief Start a transfer over a host channel * @param USBx Selected device @@ -1197,6 +1208,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) if (hc->doublebuffer == 0U) { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + /* Set RX buffer count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } @@ -1208,11 +1231,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); - /*Set the Double buffer counter*/ + /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); } - else /* switch to single buffer mode */ + else /* Switch to single buffer mode */ { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); @@ -1220,7 +1243,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } } - else /* isochronous */ + else /* Isochronous */ { /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); @@ -1228,12 +1251,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) } #endif /* USE_USB_DOUBLE_BUFFER */ - /*Enable host channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CHEP_RX_STRX); + /* Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); } else /* Out Channel */ { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (hc->xfer_len > hc->max_packet) { len = hc->max_packet; @@ -1243,17 +1266,29 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) len = hc->xfer_len; } - /* configure and validate Tx endpoint */ + /* Configure and validate Tx endpoint */ if (hc->doublebuffer == 0U) { USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); - /*SET PID SETUP */ + /* SET PID SETUP */ if ((hc->data_pid) == HC_PID_SETUP) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } } #if (USE_USB_DOUBLE_BUFFER == 1U) else if (hc->ep_type == EP_TYPE_BULK) @@ -1385,14 +1420,13 @@ static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, /** * @brief Halt a host channel in * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_DIS); return HAL_OK; } @@ -1401,17 +1435,40 @@ HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) /** * @brief Halt a host channel out * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_DIS); + + return HAL_OK; +} + +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param phy_ch_num Host Channel number + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir) +{ + if (ch_dir == CH_IN_DIR) + { + /* Enable TX host Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_VALID); + } + else + { + /* Enable RX host Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); + } return HAL_OK; } +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Stop Host Core diff --git a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c index c35ea47856..1a518d34d8 100644 --- a/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c +++ b/system/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c @@ -126,7 +126,7 @@ * @{ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); + LL_UTILS_PLLInitTypeDef const *UTILS_PLLInitStruct); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -450,7 +450,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) * the configuration information for the PLL. * @retval PLL output frequency (in Hz) */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef const *UTILS_PLLInitStruct) { uint32_t pllfreq; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 51d4e2a83f..1a099a3214 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -7,7 +7,7 @@ * STM32F3: 1.5.8 * STM32F4: 1.8.5 * STM32F7: 1.3.3 - * STM32G0: 1.4.6 + * STM32G0: 1.4.7 * STM32G4: 1.2.7 * STM32H5: 1.6.0 * STM32H7: 1.11.6 From a991ba732ede181f0b03b0469147dd6cf0b8ad37 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 May 2026 15:08:30 +0200 Subject: [PATCH 2/2] system(g0): update STM32G0xx CMSIS Drivers to v1.4.5 Included in STM32CubeG0 FW v1.6.3 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32G0xx/Include/stm32g030xx.h | 11 ++- .../Device/ST/STM32G0xx/Include/stm32g031xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g041xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g050xx.h | 11 ++- .../Device/ST/STM32G0xx/Include/stm32g051xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g061xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g070xx.h | 11 ++- .../Device/ST/STM32G0xx/Include/stm32g071xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g081xx.h | 17 ++++- .../Device/ST/STM32G0xx/Include/stm32g0b0xx.h | 14 +++- .../Device/ST/STM32G0xx/Include/stm32g0b1xx.h | 54 ++++++++++---- .../Device/ST/STM32G0xx/Include/stm32g0c1xx.h | 54 ++++++++++---- .../Device/ST/STM32G0xx/Include/stm32g0xx.h | 2 +- .../CMSIS/Device/ST/STM32G0xx/README.md | 2 +- .../Device/ST/STM32G0xx/Release_Notes.html | 74 ++++++++++++------- .../Source/Templates/system_stm32g0xx.c | 10 ++- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 17 files changed, 270 insertions(+), 77 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h index 2d51ab5392..ba40898b76 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h @@ -4037,6 +4037,12 @@ typedef struct #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */ +#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */ +#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */ +#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */ +#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */ + /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (3U) #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ @@ -4570,6 +4576,9 @@ typedef struct */ #define RTC_WAKEUP_SUPPORT #define RTC_BACKUP_SUPPORT +#define RTC_TAMP_INT_NB 4u +#define RTC_TAMP_NB 2u +#define RTC_BACKUP_NB 5u /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -6309,7 +6318,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!Purpose

Update History

- +

Main Changes

    +
  • Define the RTC_TAMP_NB, RTC_TAMP_INT_NB, and RTC_BACKUP_NB macros to improve portability.
    • +
  • Add definitions for the RCC_CFGR oscillator selection bits to simplify system clock identification.
    • +
  • Allow the VECT_TAB_OFFSET macro to be redefined via IDE settings, makefile, or command-line options.
    • +
  • Correct the definition of the TIMx_CCR5 Capture/Compare register.
    • +
  • Merge the PWR_CR2_PVMEN_USB, PWR_CR2_IOSV, and PWR_CR2_USV bits into the PWR_CR2_PVM_VDDIO2 bit, and keep the aliases to avoid breaking compatibility.
    • +
+

Contents

+
    +
  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
    • +
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
    • +
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
    • +
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
    • +
+

Known Limitations

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
  • Update USB RXBD count mask.
  • Add RCC_CFGR_SWS_HSE, HSI, PLL, LSI, LSE system clock definitions.
  • Update to support USB supply enable feature for STM32G0B0 devices.
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -70,18 +94,18 @@

Known Limitations

-

Main Changes

+

Main Changes

  • README.md update: Remove compatibility table from “Compatibility information” section.
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -90,7 +114,7 @@

Known Limitations

-

Main Changes

+

Main Changes

  • Rename ADC TRx registers AWDxTR to be compliant with the reference manual.
  • Fix Doxygen grouping issues.
    • @@ -103,14 +127,14 @@

    Main Changes

  • #define SVC_IRQn SVCall_IRQn
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -119,7 +143,7 @@

Known Limitations

-

Main Changes

+

Main Changes

  • Update to remove wrong bits defined for DMAMUX Req ID.
  • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.
    • @@ -132,14 +156,14 @@

    Main Changes

  • Update header files with new license format
-

Contents

+

Contents

  • CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.
  • CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.
  • CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.
  • CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.
-

Known Limitations

+

Known Limitations

  • None
@@ -148,7 +172,7 @@

Known Limitations

-

Main Changes

+

Main Changes

Maintenance release and Product Update

Official release for STM32G0xx CMSIS introducing stm32g0b0xx, stm32g0b1xx, stm32g0c1xx devices and stm32g050xx, stm32g051xx, stm32g061xx devices.

Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.

@@ -229,19 +253,19 @@

Maintenance release and Product -

Contents

+

Contents

-CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.

-CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.

-CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

-CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

None

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.

Fixed bugs list

@@ -257,10 +281,10 @@

Maintenance release

-

Contents

+

Contents

CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

Requirements not met or planned in a forthcoming release

@@ -290,7 +314,7 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

Maintenance release and Product Update

First release for STM32G0xx CMSIS introducing stm32g030xx, stm32g031xx, stm32g041xx devices.

Additional features

@@ -322,10 +346,10 @@

Maintenance release and Produc

-

Contents

+

Contents

CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Known Limitations

+

Known Limitations

Requirements not met or planned in a forthcoming release

@@ -358,7 +382,7 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release for STM32G0xx devices (stm32g070xx, stm32g071xx, stm32g081xx devices)

Fixed bugs list

@@ -383,17 +407,17 @@

Maintenance release

-

Contents

+

Contents

CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.

-

Main Changes

+

Main Changes

First release

First official release for STM32G0xx devices

-

Contents

+

Contents

  • CMSIS devices files for STM32G070xx, STM32G071xx and STM32G081xx
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c index 04e9098909..e56a0b35c1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c @@ -123,14 +123,16 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 2719069f86..0e7714891e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -7,7 +7,7 @@ * STM32F3: 2.3.8 * STM32F4: 2.6.11 * STM32F7: 1.2.10 - * STM32G0: 1.4.4 + * STM32G0: 1.4.5 * STM32G4: 1.2.6 * STM32H5: 1.6.0 * STM32H7: 1.10.7