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| 1 | +#ifndef _USB_XHCI_H |
| 2 | +#define _USB_XHCI_H |
| 3 | + |
| 4 | +#include <util/config.h> |
| 5 | +#include <stdint.h> |
| 6 | + |
| 7 | +/* xHCI USB速度定義 */ |
| 8 | +#define XHCI_SPEED_FULL 1 /* USB 1.1 Full Speed (12 Mbps) */ |
| 9 | +#define XHCI_SPEED_LOW 2 /* USB 1.1 Low Speed (1.5 Mbps) */ |
| 10 | +#define XHCI_SPEED_HIGH 3 /* USB 2.0 High Speed (480 Mbps) */ |
| 11 | +#define XHCI_SPEED_SUPER 4 /* USB 3.0 Super Speed (5 Gbps) */ |
| 12 | + |
| 13 | +/* xHCI Capability Registers (オフセット 0x00から) */ |
| 14 | +struct xhci_cap_regs { |
| 15 | + uint8_t caplength; /* 0x00: Capability Registers Length */ |
| 16 | + uint8_t reserved; |
| 17 | + uint16_t hciversion; /* 0x02: Interface Version Number */ |
| 18 | + uint32_t hcsparams1; /* 0x04: Structural Parameters 1 */ |
| 19 | + uint32_t hcsparams2; /* 0x08: Structural Parameters 2 */ |
| 20 | + uint32_t hcsparams3; /* 0x0C: Structural Parameters 3 */ |
| 21 | + uint32_t hccparams1; /* 0x10: Capability Parameters 1 */ |
| 22 | + uint32_t dboff; /* 0x14: Doorbell Offset */ |
| 23 | + uint32_t rtsoff; /* 0x18: Runtime Register Space Offset */ |
| 24 | + uint32_t hccparams2; /* 0x1C: Capability Parameters 2 */ |
| 25 | +}; |
| 26 | + |
| 27 | +/* xHCI Operational Registers */ |
| 28 | +struct xhci_op_regs { |
| 29 | + uint32_t usbcmd; /* 0x00: USB Command */ |
| 30 | + uint32_t usbsts; /* 0x04: USB Status */ |
| 31 | + uint32_t pagesize; /* 0x08: Page Size */ |
| 32 | + uint32_t reserved1[2]; |
| 33 | + uint32_t dnctrl; /* 0x14: Device Notification Control */ |
| 34 | + uint64_t crcr; /* 0x18: Command Ring Control Register */ |
| 35 | + uint32_t reserved2[4]; |
| 36 | + uint64_t dcbaap; /* 0x30: Device Context Base Address Array Pointer */ |
| 37 | + uint32_t config; /* 0x38: Configure */ |
| 38 | +}; |
| 39 | + |
| 40 | +/* xHCI Port Registers (Operational Registers領域内) */ |
| 41 | +struct xhci_port_regs { |
| 42 | + uint32_t portsc; /* Port Status and Control */ |
| 43 | + uint32_t portpmsc; /* Port Power Management Status and Control */ |
| 44 | + uint32_t portli; /* Port Link Info */ |
| 45 | + uint32_t porthlpmc; /* Port Hardware LPM Control */ |
| 46 | +}; |
| 47 | + |
| 48 | +/* USBCMD Register bits */ |
| 49 | +#define XHCI_CMD_RUN (1 << 0) /* Run/Stop */ |
| 50 | +#define XHCI_CMD_HCRST (1 << 1) /* Host Controller Reset */ |
| 51 | +#define XHCI_CMD_INTE (1 << 2) /* Interrupter Enable */ |
| 52 | +#define XHCI_CMD_HSEE (1 << 3) /* Host System Error Enable */ |
| 53 | +#define XHCI_CMD_EWE (1 << 10) /* Enable Wrap Event */ |
| 54 | + |
| 55 | +/* USBSTS Register bits */ |
| 56 | +#define XHCI_STS_HCH (1 << 0) /* HC Halted */ |
| 57 | +#define XHCI_STS_HSE (1 << 2) /* Host System Error */ |
| 58 | +#define XHCI_STS_EINT (1 << 3) /* Event Interrupt */ |
| 59 | +#define XHCI_STS_PCD (1 << 4) /* Port Change Detect */ |
| 60 | +#define XHCI_STS_CNR (1 << 11) /* Controller Not Ready */ |
| 61 | +#define XHCI_STS_HCE (1 << 12) /* Host Controller Error */ |
| 62 | + |
| 63 | +/* PORTSC Register bits */ |
| 64 | +#define XHCI_PORTSC_CCS (1 << 0) /* Current Connect Status */ |
| 65 | +#define XHCI_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ |
| 66 | +#define XHCI_PORTSC_PR (1 << 4) /* Port Reset */ |
| 67 | +#define XHCI_PORTSC_PLS_MASK (0xF << 5) /* Port Link State */ |
| 68 | +#define XHCI_PORTSC_PP (1 << 9) /* Port Power */ |
| 69 | +#define XHCI_PORTSC_SPEED_MASK (0xF << 10) /* Port Speed */ |
| 70 | +#define XHCI_PORTSC_CSC (1 << 17) /* Connect Status Change */ |
| 71 | +#define XHCI_PORTSC_PEC (1 << 18) /* Port Enabled/Disabled Change */ |
| 72 | +#define XHCI_PORTSC_PRC (1 << 21) /* Port Reset Change */ |
| 73 | + |
| 74 | +/* xHCI Host Controller 構造体 */ |
| 75 | +struct xhci_hc { |
| 76 | + /* MMIO Base Address */ |
| 77 | + uintptr_t base_addr; |
| 78 | + |
| 79 | + /* Register pointers */ |
| 80 | + volatile struct xhci_cap_regs *cap_regs; |
| 81 | + volatile struct xhci_op_regs *op_regs; |
| 82 | + volatile uint32_t *doorbell_array; |
| 83 | + volatile void *runtime_regs; |
| 84 | + volatile struct xhci_port_regs *port_regs; |
| 85 | + |
| 86 | + /* Controller information */ |
| 87 | + uint16_t hci_version; |
| 88 | + uint32_t max_slots; |
| 89 | + uint32_t max_ports; |
| 90 | + uint32_t max_intrs; |
| 91 | + |
| 92 | + /* PCI information */ |
| 93 | + uint8_t bus; |
| 94 | + uint8_t device; |
| 95 | + uint8_t function; |
| 96 | + |
| 97 | + /* State */ |
| 98 | + int initialized; |
| 99 | +}; |
| 100 | + |
| 101 | +/* 関数プロトタイプ */ |
| 102 | + |
| 103 | +/** |
| 104 | + * @brief PCIバスからxHCIコントローラを検出・初期化 |
| 105 | + * @return 0: 成功, 負数: エラー |
| 106 | + */ |
| 107 | +int xhci_init(void); |
| 108 | + |
| 109 | +/** |
| 110 | + * @brief xHCIコントローラをリセット |
| 111 | + * @param hc ホストコントローラ構造体 |
| 112 | + * @return 0: 成功, 負数: エラー |
| 113 | + */ |
| 114 | +int xhci_reset_controller(struct xhci_hc *hc); |
| 115 | + |
| 116 | +/** |
| 117 | + * @brief xHCIコントローラを起動 |
| 118 | + * @param hc ホストコントローラ構造体 |
| 119 | + * @return 0: 成功, 負数: エラー |
| 120 | + */ |
| 121 | +int xhci_start_controller(struct xhci_hc *hc); |
| 122 | + |
| 123 | +/** |
| 124 | + * @brief xHCIポートの状態を取得 |
| 125 | + * @param hc ホストコントローラ構造体 |
| 126 | + * @param port_num ポート番号（1から開始） |
| 127 | + * @return ポートステータス |
| 128 | + */ |
| 129 | +uint32_t xhci_get_port_status(struct xhci_hc *hc, uint32_t port_num); |
| 130 | + |
| 131 | +#endif /* _USB_XHCI_H */ |
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