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Sugar Zhangbroonie
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ASoC: rockchip: spdif: Fill IEC958 CS info per params
Add support to fill IEC958 channel status information. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patch.msgid.link/20260203-rockchip-spdif-cleanup-and-bsp-sync-v2-9-4412016cf577@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent c43ec50 commit 07a7910

3 files changed

Lines changed: 50 additions & 4 deletions

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sound/soc/rockchip/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ config SND_SOC_ROCKCHIP_SAI
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config SND_SOC_ROCKCHIP_SPDIF
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tristate "Rockchip SPDIF Device Driver"
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select SND_PCM_IEC958
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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Say Y or M if you want to add support for SPDIF driver for

sound/soc/rockchip/rockchip_spdif.c

Lines changed: 41 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include <sound/pcm_iec958.h>
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#include <sound/dmaengine_pcm.h>
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#include "rockchip_spdif.h"
@@ -27,7 +28,25 @@ enum rk_spdif_type {
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RK_SPDIF_RK3366,
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};
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#define RK3288_GRF_SOC_CON2 0x24c
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/*
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* CS0: | Mode | d | c | b | a |
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* CS1: | Category Code |
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* CS2: | Channel Number | Source Number |
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* CS3: | Clock Accuracy | Sample Freq |
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* CS4: | Ori Sample Freq | Word Length |
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* CS5: | | CGMS-A |
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* CS6~CS23: Reserved
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*
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* a: use of channel status block
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* b: linear PCM identification: 0 for lpcm, 1 for nlpcm
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* c: copyright information
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* d: additional format information
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*/
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#define CS_BYTE 6
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#define CS_FRAME(c) ((c) << 16 | (c))
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#define RK3288_GRF_SOC_CON2 0x24c
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struct rk_spdif_dev {
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struct device *dev;
@@ -88,8 +107,20 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
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struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
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unsigned int mclk_rate = clk_get_rate(spdif->mclk);
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unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
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int bmc, div;
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int ret;
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int bmc, div, ret, i;
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u16 *fc;
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u8 cs[CS_BYTE];
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ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, sizeof(cs));
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if (ret < 0)
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return ret;
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fc = (u16 *)cs;
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for (i = 0; i < CS_BYTE / 2; i++)
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regmap_write(spdif->regmap, SPDIF_CHNSRn(i), CS_FRAME(fc[i]));
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regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CSE_MASK,
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SPDIF_CFGR_CSE_EN);
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/* bmc = 128fs */
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bmc = 128 * params_rate(params);
@@ -239,6 +270,9 @@ static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
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case SPDIF_INTCR:
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case SPDIF_XFER:
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case SPDIF_SMPDR:
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case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
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case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
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case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
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return true;
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default:
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return false;
@@ -254,6 +288,9 @@ static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
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case SPDIF_INTSR:
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case SPDIF_XFER:
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case SPDIF_SMPDR:
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case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
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case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
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case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
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return true;
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default:
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return false;
@@ -276,7 +313,7 @@ static const struct regmap_config rk_spdif_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = SPDIF_SMPDR,
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.max_register = SPDIF_VERSION,
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.writeable_reg = rk_spdif_wr_reg,
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.readable_reg = rk_spdif_rd_reg,
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.volatile_reg = rk_spdif_volatile_reg,

sound/soc/rockchip/rockchip_spdif.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,10 @@
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#define SPDIF_CFGR_CLR_EN BIT(7)
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#define SPDIF_CFGR_CLR_DIS 0
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#define SPDIF_CFGR_CSE_MASK BIT(6)
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#define SPDIF_CFGR_CSE_EN BIT(6)
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#define SPDIF_CFGR_CSE_DIS 0
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#define SPDIF_CFGR_ADJ_MASK BIT(3)
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#define SPDIF_CFGR_ADJ_LEFT_J BIT(3)
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#define SPDIF_CFGR_ADJ_RIGHT_J 0
@@ -64,5 +68,9 @@
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#define SPDIF_INTSR (0x0010)
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#define SPDIF_XFER (0x0018)
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#define SPDIF_SMPDR (0x0020)
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#define SPDIF_VLDFRn(x) (0x0060 + (x) * 4)
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#define SPDIF_USRDRn(x) (0x0090 + (x) * 4)
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#define SPDIF_CHNSRn(x) (0x00c0 + (x) * 4)
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#define SPDIF_VERSION (0x01c0)
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#endif /* _ROCKCHIP_SPDIF_H */

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