1616#include <linux/mfd/syscon.h>
1717#include <linux/regmap.h>
1818#include <sound/pcm_params.h>
19+ #include <sound/pcm_iec958.h>
1920#include <sound/dmaengine_pcm.h>
2021
2122#include "rockchip_spdif.h"
@@ -27,7 +28,25 @@ enum rk_spdif_type {
2728 RK_SPDIF_RK3366 ,
2829};
2930
30- #define RK3288_GRF_SOC_CON2 0x24c
31+ /*
32+ * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
33+ * CS0: | Mode | d | c | b | a |
34+ * CS1: | Category Code |
35+ * CS2: | Channel Number | Source Number |
36+ * CS3: | Clock Accuracy | Sample Freq |
37+ * CS4: | Ori Sample Freq | Word Length |
38+ * CS5: | | CGMS-A |
39+ * CS6~CS23: Reserved
40+ *
41+ * a: use of channel status block
42+ * b: linear PCM identification: 0 for lpcm, 1 for nlpcm
43+ * c: copyright information
44+ * d: additional format information
45+ */
46+ #define CS_BYTE 6
47+ #define CS_FRAME (c ) ((c) << 16 | (c))
48+
49+ #define RK3288_GRF_SOC_CON2 0x24c
3150
3251struct rk_spdif_dev {
3352 struct device * dev ;
@@ -88,8 +107,20 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
88107 struct rk_spdif_dev * spdif = snd_soc_dai_get_drvdata (dai );
89108 unsigned int mclk_rate = clk_get_rate (spdif -> mclk );
90109 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE ;
91- int bmc , div ;
92- int ret ;
110+ int bmc , div , ret , i ;
111+ u16 * fc ;
112+ u8 cs [CS_BYTE ];
113+
114+ ret = snd_pcm_create_iec958_consumer_hw_params (params , cs , sizeof (cs ));
115+ if (ret < 0 )
116+ return ret ;
117+
118+ fc = (u16 * )cs ;
119+ for (i = 0 ; i < CS_BYTE / 2 ; i ++ )
120+ regmap_write (spdif -> regmap , SPDIF_CHNSRn (i ), CS_FRAME (fc [i ]));
121+
122+ regmap_update_bits (spdif -> regmap , SPDIF_CFGR , SPDIF_CFGR_CSE_MASK ,
123+ SPDIF_CFGR_CSE_EN );
93124
94125 /* bmc = 128fs */
95126 bmc = 128 * params_rate (params );
@@ -239,6 +270,9 @@ static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
239270 case SPDIF_INTCR :
240271 case SPDIF_XFER :
241272 case SPDIF_SMPDR :
273+ case SPDIF_VLDFRn (0 ) ... SPDIF_VLDFRn (11 ):
274+ case SPDIF_USRDRn (0 ) ... SPDIF_USRDRn (11 ):
275+ case SPDIF_CHNSRn (0 ) ... SPDIF_CHNSRn (11 ):
242276 return true;
243277 default :
244278 return false;
@@ -254,6 +288,9 @@ static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
254288 case SPDIF_INTSR :
255289 case SPDIF_XFER :
256290 case SPDIF_SMPDR :
291+ case SPDIF_VLDFRn (0 ) ... SPDIF_VLDFRn (11 ):
292+ case SPDIF_USRDRn (0 ) ... SPDIF_USRDRn (11 ):
293+ case SPDIF_CHNSRn (0 ) ... SPDIF_CHNSRn (11 ):
257294 return true;
258295 default :
259296 return false;
@@ -276,7 +313,7 @@ static const struct regmap_config rk_spdif_regmap_config = {
276313 .reg_bits = 32 ,
277314 .reg_stride = 4 ,
278315 .val_bits = 32 ,
279- .max_register = SPDIF_SMPDR ,
316+ .max_register = SPDIF_VERSION ,
280317 .writeable_reg = rk_spdif_wr_reg ,
281318 .readable_reg = rk_spdif_rd_reg ,
282319 .volatile_reg = rk_spdif_volatile_reg ,
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