@@ -156,7 +156,7 @@ static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
156156 acp_reg_write (priority_level , acp_mmio , mmACP_DMA_PRIO_0 + ch_num );
157157}
158158
159- /* Initialize a dma descriptor in SRAM based on descritor information passed */
159+ /* Initialize a dma descriptor in SRAM based on descriptor information passed */
160160static void config_dma_descriptor_in_sram (void __iomem * acp_mmio ,
161161 u16 descr_idx ,
162162 acp_dma_dscr_transfer_t * descr_info )
@@ -288,7 +288,7 @@ static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
288288 & dmadscr [i ]);
289289 }
290290 pre_config_reset (acp_mmio , ch );
291- /* Configure the DMA channel with the above descriptore */
291+ /* Configure the DMA channel with the above descriptor */
292292 config_acp_dma_channel (acp_mmio , ch , dma_dscr_idx - 1 ,
293293 NUM_DSCRS_PER_CHANNEL ,
294294 ACP_DMA_PRIORITY_LEVEL_NORMAL );
@@ -322,7 +322,7 @@ static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
322322 high |= BIT (31 );
323323 acp_reg_write (high , acp_mmio , mmACP_SRBM_Targ_Idx_Data );
324324
325- /* Move to next physically contiguos page */
325+ /* Move to next physically contiguous page */
326326 addr += PAGE_SIZE ;
327327 }
328328}
@@ -602,11 +602,11 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
602602 acp_reg_write (val , acp_mmio , mmACP_BT_UART_PAD_SEL );
603603 }
604604
605- /* initiailize Onion control DAGB register */
605+ /* initialize Onion control DAGB register */
606606 acp_reg_write (ACP_ONION_CNTL_DEFAULT , acp_mmio ,
607607 mmACP_AXI2DAGB_ONION_CNTL );
608608
609- /* initiailize Garlic control DAGB registers */
609+ /* initialize Garlic control DAGB registers */
610610 acp_reg_write (ACP_GARLIC_CNTL_DEFAULT , acp_mmio ,
611611 mmACP_AXI2DAGB_GARLIC_CNTL );
612612
@@ -621,7 +621,7 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
621621 acp_reg_write (ACP_SRAM_BASE_ADDRESS , acp_mmio ,
622622 mmACP_DMA_DESC_BASE_ADDR );
623623
624- /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
624+ /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */
625625 acp_reg_write (0x4 , acp_mmio , mmACP_DMA_DESC_MAX_NUM_DSCR );
626626 acp_reg_write (ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK ,
627627 acp_mmio , mmACP_EXTERNAL_INTR_CNTL );
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